TLC320AD80C Datasheet, PDF (22/36 Pages) Texas Instruments – Audio Processor Subsystem

2.5.3 Power-Down/Reset
When the RESET terminal is held low, the TLC320AD80C is put in a power-down condition. During power
down, the sigma-delta DACs are disabled to conserve power and the digital output drivers (ABCLK,
ALRCLK, and CDOUT) are placed in a high-impedance state. When powered down, the analog audio
outputs settle near V_ref (2.25 V).
There are two ways in which to initialize the TLC320AD80C.
• The TLC320AD80C begins reset and initialization on the rising edge of the RESET signal. A
stable clock waveform having a frequency within the specified allowable frequency range (see
Timing Requirements section) must be present at the master clock (MCLK1) input prior to the
rising edge of the RESET signal for proper operation. In order to prevent the occurrence of
audible pops or clicks from the TLC320AD80C, the RESET terminal must be kept low 500 ms
after the power supplies have settled. This provides adequate time for the 2.25-V based line
outputs to charge the large output capacitors on the analog audio outputs while minimizing any
audible pops.
• Set bit D0 of control register 02h to 1.
To maximize the initialization cycle accuracy, the TLC320AD80C should not be continually polled. This
initialization cycle takes about 500 ms to complete following the rising edge of RESET.
The power-down mode can also be selected by setting bit D0 of control register 02h to 1. In this software
controlled power-down mode the sigma-delta DACs, the monaural decoder, and the audio input amplifiers
are all disabled to conserve power. The external audio outputs (EXT OUTR, EXT OUTL) are muted to hold
the output voltage at V_ref. Since muting the external audio output can cause an audible click, a zero crossing
mute should be performed prior to initiating a software power-down.
2.6 Software Interface
Control of the TLC320AD80 is accomplished by means of the SPI serial interface and the control registers
described in Appendix A.
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