TLC320AD80C Datasheet, PDF (14/36 Pages) Texas Instruments – Audio Processor Subsystem

2.1.1.1 Main Serial PCM Port
The main serial PCM (SDATA, BCLK, and LRCLK) port always operates in slave mode. That is, all clocks
are inputs to the device. The LRCLK and BCLK clocks must be synchronous with MCLK.
A typical set-top-box application would connect this input to an MPEG/AC3 audio decoder.
2.1.1.2 Aux Serial PCM Data Port
The aux serial port (ASDATA, ABCLK, and ALRCLK) operates in either the master or slave mode. The
master mode supports all the documented interface protocols with the exception of the DSP mode. The
slave mode supports all documented protocols without exception.
The aux serial PCM data port receives non-compressed data from an auxillary audio source. The slave
mode is identical to the clock mode of main serial PCM port. In the master mode, this device generates the
required BCLK and LRCLK clocks synchronously with the applied MCLK.
2.1.1.3 Serial Interface Protocols Supported
The serial ports comprise the signals in Table 2–1.
MAIN PORT
SDATA
BCLK
LRCLK
AUXILIARY PORT
ASDATA
ABCLK
ALRCLK
Table 2–1. Serial Port Signals
DESCRIPTION
PCM audio data. 16-bit or 18-bit data precision
Bit clock. Rate is equal to 32x, 48x, or 64x the sample rate
Left/right clock. Rate is equal to the sample rate
Figure 2–1 through Figure 2–4 are for a bit clock (BCLK) set to 48 the sample rate and 16-bit data
precision. All serial protocols supported are shown.
LRCLK
Left Channel
Right Channel
BCLK
SDATA
16 Bit ^{X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X}
SDATA
18 Bit ^{X X X 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X}
Figure 2–1. Philips I²S Protocol Serial PCM Data Format
LRCLK
Left Channel
Right Channel
BCLK
SDATA
16 Bit ^{X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X}
SDATA
X X 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X
18 Bit
Figure 2–2. Left-Justified Serial PCM Data Format
2–3