TLC2942 Datasheet, PDF (22/28 Pages) Texas Instruments – HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
basic design example
The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.
Assume the loop has to have a 100-µs settling time (t_s) with a countdown divider N value = 8. Using the Type
1, second-order response curves of Figure 26, a value of 4.5 radians is selected for ω_nt_s with a damping factor
of 0.7. This selection gives a good combination for settling time, accuracy, and loop gain margin. The initial
parameters are summarized in Table 7. The loop constants, K_V and K_p, are calculated from the data sheet
specifications and Table 8 shows these values.
The natural loop frequency is calculated as follows:
Since
+ w_nts 4.5
(4)
Then
+ + ń w _{m n}
4.5
100 s
45 k-radians sec
Table 7. Design Parameters
PARAMETER
Divider value
Lockup time
Radian value to selected lockup time
Damping factor
SYMBOL
N
t
ω_nt
ζ
VALUE
8
100
4.5
0.7
UNITS
µs
rad
Table 8. Device Specifications
PARAMETER
VCO gain
fMAX
fMIN
VIN _MAX
VIN _MIN
PFD gain
SYMBOL
KV
Kp
VALUE
76.6
70
20
5
0.9
0.342357
UNITS
Mrad/V/s
MHz
MHz
V
V
V/rad
Using the low-pass filter in Figure 25(b) and divider N value, the transfer function for phase and frequency are
shown in equations 5 and 6. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.
Hence, transfer function of Figure 24 (a) for phase is:
@ ^{@ ȧȧȧȱȲ} _{ƪ @ @@ @} ^{ȳȧȧ + ) F2(s)}
@ ^ƫ @ _ȴȧ ^F1(s)
Kp KV
N (T1 T2)
) s2 s
)1 s T2
) ₎ ) ₎ 1
Kp KV T2
N (T1 T2)
Kp KV
N (T1 T2)
(5)
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