TLC2942 Datasheet, PDF (18/28 Pages) Texas Instruments – HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired VCO output frequency according
to the system application requirements. The K_p
and K_V values are obtained from the operating
characteristics of the device as shown in Figure
24. K_p is defined from the phase detector V_OL and
fREF
V_OH specifications and the equation shown in
Figure 24(b). K_V is defined from Figures 8, 9, 10,
and 11 as shown in Figure 24(c).
The parameters for the block diagram with the
units are as follows:
Divider
(KN = 1/N)
PFD
(Kp)
TLC2942
VCO
(KV)
LPF
(Kf)
(a)
VOH
K_V : VCO gain (rad/s/V)
K_p : PFD gain (V/rad)
K_f : LPF gain (V/V)
K_N : countdown divider gain (1/N)
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
R_BIAS
– 2π – π 0 π 2π
fMAX
VOH
VOL ^fMIN
Range of
Comparison
VIN _MIN
VIN _MAX
Kp =
VOH – VOL
4π
(b)
KV =
2π(fMAX – fMIN)
VIN _MAX – VIN _MIN
(c)
Figure 24. Example of a PLL Block Diagram
The external bias resistor sets the VCO center frequency with 1/2 V_DD applied to the VCOIN terminal. However,
for optimum temperature performance, a resistor value of 3.3 kΩ with a 3-V supply, or a resistor value of
2.5 kΩ for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice,
but a carbon-compositiion resistor can be used with excellent results also. A 0.22-µF capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
] ǒ Ǔ ǒ Ǔ ǒ R Ǔ configurations shown in Figure 25 is as follows:
Dw_H 0.8 Kp KV Kf ( )
(1)
Where
K_f (∞) = the filter transfer function value at ω = ∞
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