THS4281 Datasheet, PDF (22/31 Pages) Texas Instruments – VERY LOW-POWER, HIGH-SPEED, RAIL-TO-RAIL INPUT AND OUTPUT VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER

THS4281
SLOS432 – APRIL 2004
Power Supply Decoupling Techniques and
Recommendations
Power supply decoupling is a critical aspect of any
high-performance amplifier design. Careful decoup-
ling provides higher quality ac performance. The
following guidelines ensure the highest level of per-
formance.
1. Place decoupling capacitors as close to the
power supply inputs as possible, with the goal of
minimizing the inductance.
2. Placement priority should put the smallest valued
capacitors closest to the device.
3. Use of solid power and ground planes is rec-
ommended to reduce the inductance along power
supply return current paths (with the exception of
the areas underneath the input and output pins
as noted below).
4. A bulk decoupling capacitor is recommended (6.8
to 22 µF) within 1 inch, and a ceramic (0.1 µF)
within 0.1 inch of the power input pins.
NOTE:
The bulk capacitor may be
shared by other op amps.
BOARD LAYOUT
Achieving optimum performance with a high fre-
quency amplifier like the THS4281 requires careful
attention to board layout parasitics and external
component types. See the EVM layout figures in the
Design Tools Section.
Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability and on the noninverting
input, it can react with the source impedance to
cause unintentional band limiting. To reduce un-
wanted capacitance, a window around the signal
I/O pins should be opened in all of the ground
and power planes around those pins. Otherwise,
ground and power planes should be unbroken
elsewhere on the board.
2. Minimize the distance (< 0.1 inch) from the
power supply pins to high frequency 0.1-µF
decoupling capacitors. Avoid narrow power and
ground traces to minimize inductance. The power
supply connections should always be decoupled
as described above.
3. Careful selection and placement of external
components preserves the high frequency
performance of the THS4281. Resistors should
be a low reactance type. Surface-mount resistors
work best and allow a tighter overall layout.
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Metal-film, axial-lead resistors can also provide
good high frequency performance. Again, keep
their leads and PC board trace length as short as
possible. Never use wire wound type resistors in
a high frequency application. Because the output
pin and inverting input pin are the most sensitive
to parasitic capacitance, always position the
feedback and series output resistor, if any, as
close as possible to the output pin. Other network
components, such as noninverting input termin-
ation resistors, should also be placed close to the
package. Excessively high resistor values can
create significant phase lag that can degrade
performance. Keep resistor values as low as
possible, consistent with load-driving consider-
ations. It is suggested that a good starting point
for design is to set the R_f to 2 kΩ for low-gain,
noninverting applications. Doing this automati-
cally keeps the resistor noise terms reasonable
and minimizes the effect of parasitic capacitance.
4. Connections to other wideband devices on
the board should be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and set R_ISO from the
plot of recommended R_ISO vs capacitive load.
Low parasitic capacitive loads (<4 pF) may not
need an R_(ISO), because the THS4281 is nom-
inally compensated to operate at unity gain (+1
V/V) with a 2-pF capacitive load. Higher capaci-
tive loads without an R_(ISO) are allowed as the
signal gain increases. If a long trace is required,
and the 6-dB signal loss intrinsic to a doubly
terminated transmission line is acceptable, im-
plement a matched impedance transmission line
using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and
stripline layout techniques). A matching series
resistor into the trace from the output of the
THS4281 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device:
this total effective impedance should be set to
match the trace impedance. If the 6-dB attenu-
ation of a doubly terminated transmission line is
unacceptable, a long trace can be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case, and
set the series resistor value as shown in the plot
of R_(ISO) vs capacitive load. If the input im-
pedance of the destination device is low, there is
signal attenuation due to the voltage divider
formed by R_(ISO) into the terminating impedance.