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THS4281 Datasheet, PDF (20/31 Pages) Texas Instruments – VERY LOW-POWER, HIGH-SPEED, RAIL-TO-RAIL INPUT AND OUTPUT VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER
THS4281
SLOS432 – APRIL 2004
WIDEBAND, INVERTING OPERATION
Figure 71 shows a typical inverting configuration
where the input and output impedances and noise
gain from Figure 68 are retained with an inverting
circuit gain of -1 V/V.
+VS
CT
0.1 µF
+
RT
1.24 kΩ _
50-Ω Source
Rg
VI
2.49 kΩ
RM
51.1 Ω
Rf
2.49 kΩ
+
0.1 µF 6.8 µF
VO
To Load
0.1 µF 6.8 µF
+
−VS
Figure 71. Wideband, Inverting Gain
Configuration
In the inverting configuration, some key design con-
siderations must be noted. One is that the gain
resistor (Rg) becomes part of the signal channel input
impedance. If the input impedance matching is de-
sired (which is beneficial whenever the signal is
coupled through a cable, twisted pair, long PC board
trace, or other transmission line conductors), Rg may
be set equal to the required termination value and Rf
adjusted to give the desired gain. However, care
must be taken when dealing with low inverting gains,
as the resultant feedback resistor value can present a
significant load to the amplifier output. For example,
an inverting gain of 2, setting Rg to 49.9 Ω for input
matching, eliminates the need for RM but requires a
100-Ω feedback resistor. The 100-Ω feedback re-
sistor, in parallel with the external load, causes
excessive loading on the amplifier output. To elimin-
ate this excessive loading, it is preferable to increase
both Rg and Rf values, as shown in Figure 71, and
then achieve the input matching impedance with a
third resistor (RM) to ground. The total input im-
pedance is the parallel combination of Rg and RM.
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Another consideration in inverting amplifier design is
setting the bias current cancellation resistor (RT) on
the noninverting input. If the resistance is set equal to
the total dc resistance presented to the device at the
inverting terminal, the output dc error (due to the
input bias currents) is reduced to the input offset
current multiplied by RT. In Figure 71, the dc source
impedance presented at the inverting terminal is 2.49
kΩ || (2.49 kΩ + 25.3 Ω) ≅ 1.24 kΩ. To reduce the
additional high-frequency noise introduced by the
resistor at the noninverting input, RT is bypassed with
a 0.1-µF capacitor to ground (CT).
SINGLE-SUPPLY OPERATION
The THS4281 is designed to operate from a single
2.7-V to 16.5-V power supply. When operating from a
single power supply, care must be taken to ensure
the input signal and amplifier are biased appropriately
to allow for the maximum output voltage swing and
not violate VICR. The circuits shown in Figure 72
shows inverting and noninverting amplifiers con-
figured for single-supply operation.
+VS
50-Ω Source
+
VI
RT 49.9 Ω _
VO
+VS
2
Rg
2 kΩ
+VS
2
To Load
Rf
2 kΩ
Power Supply Bypassing
Not Shown For Simplicity
Rf
50-Ω Source
Rg
VI
51.1 Ω
2 kΩ
RT
RT
2 kΩ
VS
_
+
+VS
+VS
2
2
CT
VO
To Load
Figure 72. DC-Coupled Single Supply Operation
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