DDC112Y Datasheet, PDF (22/34 Pages) Texas Instruments – Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

CLK
DVALID
DXMIT
DCLK⁽¹⁾
DIN
t₁₈
t₁₄
t₂₀
t₂₂
t₂₄
DOUT
t₂₁
Output Disabled
t_22A, t_22B
Input A
Bit 1
MSB
Output Enabled
Input E
Bit 20
LSB
Input F
Bit 1
MSB
NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH.
t₂₆
t₂₅
Input F
Bit 20
LSB
t₂₃
Output Disabled
FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112.
CLK = 10MHz
SYMBOL
DESCRIPTION
MIN
TYP
MAX
t₂₄
Set-Up Time From DIN to Rising Edge of DCLK
10
t₂₅
Hold Time For DIN After Rising Edge of DCLK
10
t₂₆
Hold Time for DXMIT HIGH Before Falling
2
Edge of DVALID
TABLE X. Timing for the DDC112 Data Retrieval Using DIN.
CLK = 15MHz
MIN
TYP
MAX
5
10
1.33
UNITS
ns
ns
µs
RETRIEVAL BEFORE CONV TOGGLES
(CONTINUOUS MODE)
This is the most straightforward method. Data retrieval be-
gins soon after DVALID goes LOW and finishes before
CONV toggles, see Figure 24. For best performance, data
retrieval must stop t₂₈ before CONV toggles. This method is
the most appropriate for longer integration times. The maxi-
mum time available for readback is T_INT – t₂₇ – t₂₈.
For DCLK and CLK = 10MHz, the maximum number of
DDC112s that can be daisy-chained together is:
T_INT – 431.2µs
40τ_DCLK
Where τ_DCLK is the period of the data clock. For example, if
T_INT = 1000µs and DCLK = 10MHz, the maximum number of
DDC112s is:
1000µs – 431.2µs _{= 142.2 → 142 DDC112s}
(40)(100ns)
RETRIEVAL AFTER CONV TOGGLES
(CONTINUOUS MODE)
For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the new
data is ready. Data retrieval must wait t₂₉ after CONV toggles
before beginning. Figure 25 shows an example of this. The
maximum time available for retrieval is t₂₇ – t₂₉ – t₂₆
(421.2µs – 10µs – 2µs for CLK = 10MHz), regardless of T_INT.
The maximum number of DDC112s that can be daisy-
chained together is:
409.2µs
40τ_DCLK
For DCLK = 10MHz, the maximum number of DDC112s is
102.
22
DDC112
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