DDC112Y Datasheet, PDF (20/34 Pages) Texas Instruments – Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

SPECIAL CONSIDERATIONS
NCONT MODE INTEGRATION TIME
The DDC112 uses a relatively fast clock. For CLK = 10MHz,
this allows T_INT to be adjusted in steps of 100ns since CONV
should be synchronized to CLK. However, for the internal
measurement, reset and auto-zero operations, a slower
clock is more efficient. The DDC112 divides CLK by six and
uses this slower clock with a period of 600ns to run the m/r/
az cycle and data ready logic.
Because of the divider, it is possible for the integration time
to be a non-integer number of slow clock periods. For
example, if T_INT = 5000 CLK periods (500µs for CLK = 10MHz),
there will be 833 1/3 slow clocks in an integration period. This
non-integer relationship between T_INT and the slow clock
period causes the number of rising and falling slow clock
edges within an integration period to change from integration
to integration. The digital coupling of these edges to the
integrators will in turn change from integration to integration
which produces noise. The change in the clock edges is not
random, but will repeat every 3 integrations. The coupling
noise on the integrators appears as a tone with a frequency
equal to the rate at which the coupling repeats.
To avoid this problem in cont mode, the internal slow clock
is shut down after the m/r/az cycle is complete when it is no
longer needed. It starts up again just after the next integra-
tion begins. Since the slow clock is always off when CONV
toggles, the same number of slow clock edges fall within an
integration period regardless of its length. Therefore,
T_INT ≥ 4794 CLK periods will not produce the coupling
problem described above.
For the ncont mode however, the slow clock must always be
left running. The m/r/az cycle is not completed before an
integration ends. It is then possible to have digital coupling to
the integrators. The digital coupling noise depends heavily on
the layout of the printed circuit board used for the DDC112.
For solid grounds and power supplies with good bypassing,
it is possible to greatly reduce the coupling. However, for
ensuring the best performance in the ncont mode, the inte-
gration time should be chosen to be an integer multiple of
1/(2f_SLOWCLOCK). For CLK = 10MHz, the integration time
should be an integer multiple of 300ns—T_INT = 100µs is not.
A better choice would be T_INT = 99µs.
DATA READY
The DVALID signal which indicates that data is ready is
generated using the internal slow clock. The phase relation-
ship between this clock and CLK is set when power is first
applied and is random. Since CONV is synchronized with
CLK, it will have a random phase relationship with respect to
the slow clock. When T_INT > t₆, the slow clock will temporarily
shut down as described above. This shutdown process
synchronizes the internal clock with CONV so that the time
between when CONV toggles to when DVALID goes LOW
(t₇ and t₈) is fixed.
For T_INT ≤ t₆, the internal slow clock, is not allowed to shut
down and the synchronization never occurs. Therefore, the
time between CONV toggling and DVALID indicating data is
ready has uncertainty due to the random phase relationship
between CONV and the slow clock. This variation is
±1/(2f_SLOWCLOCK) or ±3/f_CLK. The timing to the second DVALID
in the ncont mode will not have a variation since it is
triggered off the first data ready (t₉) and both are derived
from the slow clock.
Polling DVALID to determine when data is ready eliminates
any concern about the variation in timing since the readback
is automatically adjusted as needed. If the data readback is
triggered off the toggling of CONV directly (instead of poll-
ing), then waiting the maximum value of t₇ or t₈ insures that
data will always be ready before readback occurs.
Data Retrieval
In the continuous and noncontinuous modes of operation,
the data from the last conversion is available for retrieval with
the falling edge of DVALID (see Figure 22). The falling edge
of DXMIT in combination with the data clock (DCLK) will
initiate the serial transmission of the data from the DDC112.
Typically, data is retrieved from the DDC112 as soon as
DVALID falls and completed before the next CONV transition
from HIGH to LOW or LOW to HIGH occurs. If this is not the
case, care should be taken to stop activity on DCLK and
consequently DOUT by at least 10µs around a CONV tran-
sition. If this caution is ignored it is possible that the integra-
tion that is being initiated by CONV will have additional noise
introduced.
The serial output data at DOUT is transmitted in Straight
Binary Code per Table VIII. An output offset has been built
into the DDC112 to allow for the measurement of input
signals near and below zero. Board leakage up to ≈ –0.4%
of the positive full-scale can be tolerated before the digital
output clips to all zeroes.
CODE
1111 1111 1111 1111 1111
1111 1111 1111 1111 1110
0000 0001 0000 0000 0001
0000 0001 0000 0000 0000
0000 0000 0000 0000 0000
INPUT SIGNAL
FS
FS – 1LSB
+1LSB
Zero
–0.4% FS
TABLE VIII. Straight Binary Code Table.
Cascading Multiple Converters
Multiple DDC112 units can be connected in serial or parallel
configurations, as illustrated in Figures 20 and 21.
DOUT can be used with DIN to daisy-chain several DDC112
devices together to minimize wiring. In this mode of opera-
tion, the serial data output is shifted through multiple DDC112s,
as illustrated in Figure 20.
R_PULLUP prevents DIN from floating when DXMIT is HIGH.
Care should be taken to keep the capacitive load on DOUT
as low as possible when running CLK=15MHz.
20
DDC112
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