BQ2023 Datasheet, PDF (22/27 Pages) Texas Instruments – SINGLE-WIRE ADVANCED BATTERY MONITOR IC FOR CELLULAR AND PDA APPLICATIONS

bq2023
SINGLEĆWIRE ADVANCED BATTERY MONITOR IC
FOR CELLULAR AND PDA APPLICATIONS
SLUS480B – MAY 2001
APPLICATION INFORMATION
register descriptions (continued)
STC and STD The slow time charge (STC) and slow time discharge (STD) flags indicate if the CTC or DTC
registers have rolled over beyond FFFF hex. STC set to 1 indicates a CTC rollover; STD set to 1 indicates a
DTC rollover. These bits are in indeterminate states on power-on-reset.
WOE[2..0] The wake-up output enable (WOE) bits (bits 3–1) set the wake-up enable signal level.
Whenever |V_SRP– V_SRN |<V_WOE, and the SLEN bit is set the bq2023 will enter sleep mode, after approximately
one hour of inactivity on SDQ pin. Setting all of these bits to zero will cause the device to sleep if SLEN is set
and there is no SDQ activity, regardless of V_SRP-V_SRN voltage. Refer to Table 3 for the various WOE values.
All WOE bits are set to 1 on power-on-reset.
RSVD
BIT0 is a reserved bit and must always be set to 0. This bit is cleared on power-on-reset.
clear register (CLR)
As described in the table below, the bits in the CLR register (address 0104 hex) clear the DCR, CCR, SCR, DTC
and CTC registers, determine if a power-on-reset occurred, and set the state of the STAT pin.
7
RSVD
6
POR
5
STAT
CLR BITS
4
3
CTC DTC
2
SCR
1
CCR
0
DCR
RSVD Reserved for future use.
POR
The POR bit (bit 6) indicates a power-on-reset has occurred. This bit is set when VCC has gone
below the POR level. This bit can be set and cleared by the host, but setting has no effect.
STAT The STAT bit (bit 5) sets the state of the open drain output of the STAT pin. A 1 turns off the open
drain output while a 0 turns the output on. This bit is set to a 1 on power-on-reset.
CTC
The CTC bit (bit 4) clears the CTCH, CTCL registers and the STC bit. A 1 clears the corresponding
registers and bit. After the registers are cleared, the CTC bit is cleared. This bit is cleared on power-on-reset.
DTC
The DTC bit (bit 3) clears the DTCH, DTCL registers and the STD bit. A 1 clears the corresponding
registers and bit. After the registers are cleared, the DTC bit is cleared. This bit is cleared on power-on-reset.
SCR
The SCR bit (bit 2) clears both the SCRH and SCRL registers. Writing a 1 to this bit clears the SCRH
and SCRL register. After these registers are cleared, the SCR bit is cleared. This bit is cleared on
power-on-reset.
CCR
The CCR bit (bit 1) clears both the CCRH and CCRL registers. Writing a 1 to this bit clears the CCRH
and CCRL registers. After these registers are cleared, the CCR bit is cleared. This bit is cleared on
power-on-reset.
DCR
The DCR bit (bit 0) clears both the DCRH and DCRL registers to 0. Writing a 1 to this bit clears the
SCRH and SCRL register. After these registers are cleared, the SCR bit is cleared. This bit is cleared on
power-on-reset.
temperature registers
The TMPH register (address 0103 hex) and the TMPL register (address 0102 hex) report die temperature in
hex format in increments of 0.25°K. These read-only temperature registers count at 1 count/0.25K. The read
at 25°C (i.e., 298°K) will be 0x4A8 hex.
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