AM3505_15 Datasheet, PDF (214/223 Pages) Texas Instruments – AM3517, AM3505 Sitara™ Processors

AM3517, AM3505
SPRS550F – OCTOBER 2009 – REVISED JULY 2014
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Table 6-160. JTAG Switching Characteristics Adaptive Clock Mode⁽¹⁾
NO. PARAMETER
1.8 V
MIN
MAX
3.3 V
MIN
MAX
JA1
t_c(rtck)
Cycle time
JA2
t_w(rtckL)
Typical pulse duration, jtag_rtck low
JA3
t_w(rtckH)
Typical pulse duration, jtag_rtck high
t_dc(rtck)
Duty cycle error, jtag_rtck
t_j(rtck)
Jitter standard deviation
t_R(rtck)
Rise time, jtag_rtck
t_F(rtck)
Fall time, jtag_rtck
JA11 t_{d(rtckL-tdoV)}
Delay time, jtag_rtck low to jtag_tdo valid
t_R(tdo)
Rise time, jtag_tdo,
t_F(tdo)
Fall time, jtag_tdo
(1) The jitter probability density can be approximated by a Gaussian function.
20
10
10
-2500
-14.6
2500
33.33
4
4
14.6
4
4
20
10
10
-2500
-14.6
2500
33.33
4
4
14.6
4
4
UNIT
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
jtag_tck
jtag_tdi
jtag_tms
jtag_rtck
jtag_tdo
JA4
JA5
JA6
JA7
JA8
JA9
JA10
JA1
JA2
JA3
JA11
Figure 6-74. JTAG Interface Timing Adaptive Clock Mode
030-114
214 Timing Requirements and Switching Characteristics
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