SLUA159 Datasheet, PDF (21/28 Pages) Texas Instruments – Zero Voltage Switching Resonant Power Conversion

APPLICATION NOTE
Fault Protection - Soft Start & Restart
Delay One of the unique features of the UC
3861 family of resonant mode controllers can
be found in its fault management circuitry. A
single pin connection interfaces with the soft
start, restart delay and programmable fault
mode protection circuits. In most applications,
one capacitor to ground will provide full pro-
tection upon power-up and during overload
conditions. Users can reprogram the timing
relationships or add control features (latch off
following fault, etc) with a single resistor.
Selected for this application is a 1 uF soft-
restart capacitor value, resulting in a soft-start
duration of 10 ms and a restart delay of ap-
proximately 200 ms. The preprogrammed ratio
of 19:l (restart delay to soft start) will be uti-
lized, however the relevant equations and
relationships have also been provided for other
applications. Primary current will be utilized as
the fault trip mechanism, indicative of an
overload or short circuit current condition. A
current transformer is incorporated to maxi-
mize efficiency when interfacing to the three
volt fault threshold.
Optional Programming of Tss and Tm :
Soft Start: Tss = CSR. 10K
Restart Delay: Tm = CsR. 1 9 O K
Timing Ratio: Tm:Tss = 1 9 : l
Gate Drive: Another unique feature of the
UC 3861-64 family of devices is the optimal
utilization of the silicon devoted to output
totem pole drivers. Each controller uses two
pins for the A and B outputs which are inter-
nally configured to operate in either unison or
in an alternating configuration. Typical perfor-
mance for these 1 Amp peak totem pole out-
puts shows 30 ns rise and fall times into 1 n F .
Loop Compensation -- General Information.
The ZVS technique is similar to that of con-
ventional voltage mode square wave conversion
which utilizes a single voltage feedback loop.
Unlike the dual loop system of current mode
control, the ZVS output filter section exhibits
U-138
Fig. 28 -- Programming Tss and TRD
FAULT
Fig. 29 -- Fault Operational Waveforms
a two pole-zero pair and is compensated ac-
cordingly. Generally, the overall loop is de-
signed to cross zero dB at a frequency below
one-tenth that of the switching frequency. In
this variable frequency converter, the lowest
conversion frequency will apply, corresponding
to approximately 85 KHz, for a zero crossing of
8.5 KHz. Compensation should be optimized
for the highest low frequency gain in addition
to ample phase margin at crossover. Typical
examples utilize two zeros in the error amplifi-
er compensation at a frequency equal to that of
the output filter’s two pole break. An addition-
al high frequency pole is placed in the loop to
combat the zero due to the output capacitance
ESR, assuming adequate error amplifier gain-
bandwidth.
A noteworthy alternative is the use of a two
loop approach which is similar to current mode
control, eliminating one of the output poles.
One technique known as Multi-Loop Control
for Quasi-Resonant Converters [18] has been
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