TPA2051D3 Datasheet, PDF (20/33 Pages) Texas Instruments – 2.9 W/Channel Mono Class-D Audio Subsystem with DirectPath™ Headphone Amplifier & SpeakerGuard™

TPA2051D3
SLOS641 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com
OPERATION WITH DELAYED DVDD SUPPLY
In case the DVDD supply can not be available within t_pws(refer to Figure 3) use the supply of TPA2051D3 (AVDD
or PVDD) to power up DVDD. Refer to Figure 39 for an application diagram. The TPA2051D3 DVDD supply
must be less than or equal to SDA/SCL V_IH. SDA/SCL V_IH can be higher than DVDD but must be lower than
PVDD.
DVDD
BB IC
SCL
SDA
GPIO (EN)
PVDD/AVDD
DVDD
TPA2051D3
SCL
SDA
EN
8Ω Dual-Mode
Speaker
Stereo
Headphone Jack
Figure 39. Operation With Delayed DVDD Supply
SHUTDOWN CONTROL AND POWER MANAGEMENT
Power management for the TPA2051D3 is divided into four sections: Class-D power amplifier, headphone left
amplifier, headphone right amplifier, and bypass mode. Each section has its own enable bit in the Amplifier
Control byte (Register 1). Set Register 1, Bits 3 through 0 to logic low to turn off the amplifier via software
control.
The software shutdown mode can also be achieved by changing the SWS to logic high (Register 1, Bit 4). This
will turn off all sections of the amplifier and also the reference and bias circuitry, regardless of the settings on
Register 1, Bits 3 through 1.
For lowest current consumption in shutdown mode change the EN pin to logic low or change SWS to logic HIGH.
This will turn off all sections of the amplifier including reference, and bias.
All register contents are maintained provided the supply voltage is not powered down. On supply power-down, all
information programmed into the registers by the user is lost, returning all registers back to their default state
once power is reapplied.
Charge Pump Enable
The charge pump generates a negative voltage supply for the headphone amplifiers. This allows a 0 V bias on
the amplifier outputs, eliminating the need for an output coupling capacitor. The charge pump will automatically
activate if either the HPL_Enable or HPR_Enable bits are set to logic high.
Class-D Output Amplifier
The input to the Class-D amplifier is always a mono sum (L + R) of the mux output, regardless of mux mode. Set
the Spk_Enable bit (Register 1, Bit 1) to logic high to enable the Class-D power amplifier. The Class-D amplifier
draws 4.9 mA of typical supply current when active and less than 1 µA when deactivated.
The gain of the Class-D amplifier can be selected between +6 dB and +12 dB. Set register 5 bit 7 to logic low to
select a gain of +6 dB and to logic high to select a gain of +12 dB.
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