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TPA2051D3 Datasheet, PDF (16/33 Pages) Texas Instruments – 2.9 W/Channel Mono Class-D Audio Subsystem with DirectPath™ Headphone Amplifier & SpeakerGuard™
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TPA2051D3
SLOS641 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com
bit. The master then sends the internal memory address byte, after which the TPA2051D3 issues an
acknowledge bit. The master device transmits another start condition followed by the TPA2051D3 address and
the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the TPA2051D3
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Start
Condition
Acknowledge
Repeat Start
Condition
Acknowledge
Acknowledge
Not
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A0 ACK
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I2C Device Address and
Read/Write Bit
Register
I2C Device Address and
Read/Write Bit
Figure 37. Single-Byte Read Transfer
Data Byte
Stop
Condition
MULTIPLE-BYTE READ
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA2051D3 to the master device as shown in Figure 38. With the exception of the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
Start
Condition
Acknowledge
Repeat Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6 A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
Register
I2C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Figure 38. Multiple-Byte Read Transfer
Last Data Byte
Stop
Condition
REGISTER MAPS
REGISTER BIT7
0 Version[3]
1 LIM_SEL
2 ATK_time[4]
3 REL_time[4]
4 Mode[2]
5 SPK_Gain
6 HP_Gain[2]
BIT6
Version[2]
LIM_EN
ATK_time[3]
REL_time[3]
Mode[1]
HP_0dB
HP_Gain[1]
BIT5
Version[1]
Reserved
ATK_time[2]
REL_time[2]
Mode[0]
Reserved
HP_Gain[0]
BIT4
Version[0]
SWS
ATK_time[1]
REL_time[1]
MON_Vol[4]
ST1_Vol[4]
ST2_Vol[4]
BIT3
Reserved
HPL_Enable
ATK_time[0]
REL_time[0]
MON_Vol[3]
ST1_Vol[3]
ST2_Vol[3]
BIT2
Reserved
HPR_Enable
LIMSPK[2]
LIMHP[2]
MON_Vol[2]
ST1_Vol[2]
ST2_Vol[2]
BIT1
Spk_Fault
Spk_Enable
LIMSPK[1]
LIMHP[1]
MON_Vol[1]
ST1_Vol[1]
ST2_Vol[1]
BIT0
Thermal
VM_Bypass
LIMSPK[0]
LIMHP[0]
MON_Vol[0]
ST1_Vol[0]
ST2_Vol[0]
Bits labeled “Reserved” are reserved for future enhancements. They may not be written to as it may change the
function of the device. If read, these bits may assume any value.
The TPA2051D3 I2C address is 0xE0 (binary 11100000) for writing and 0xE1 (binary 11100001) for reading.
Refer to the General I2C Operation section for more details
Fault Register (Address: 0)
BIT
Function
Reset Value
7
Version[3]
0
6
Version[2]
0
5
Version[1]
0
4
Version[0]
0
3
Reserved
0
2
Reserved
0
1
Spk_Fault
0
0
Thermal
0
16
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