SN74LVT8986_07 Datasheet, PDF (20/54 Pages) Texas Instruments – 3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759E – OCTOBER 2002 – REVISED MAY 2007
www.ti.com
ARCHITECTURE
Blocks for linking shadow protocol receive and linking shadow protocol transmit are responsible for receipt of
select protocol and transmission of acknowledge protocol, respectively. Connect control block monitors the
primary TAP state to enable receipt/acknowledge of shadow protocols in appropriate states (namely, the stable,
non-shift TAP states: Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR). Upon receipt of a valid
shadow protocol, this block performs the address and position matching required to compute the
shadow-protocol result.
Based on the linking shadow protocol result or protocol bypass (BYP₄–BYP₀) inputs, the connect control block
configures the secondary TAP network. In conjunction, it also sets the states of and CON₂–CON₀ outputs.
TAP-State Monitor
The TAP-state monitor is a synchronous finite-state machine that monitors the primary TAP state. The state
diagram is shown in Figure 4 and mirrors that specified by IEEE Std 1149.1. The TAP-state monitor proceeds
through its states based on the level of PTMS at the rising edge of PTCK. Each state is described both in terms
of its significance for LASP devices and for connected IEEE Std 1149.1-compliant devices (called targets).
However, the monitor state (primary TAP) can be different from that of disconnected scan chains (secondary
TAP).
TEST-LOGIC-RESET
The LASP TAP-state monitor powers up in the Test-Logic-Reset state. Alternatively, the LASP can be forced
asynchronously to this state by assertion of its PTRST input. In the stable Test-Logic-Reset state, the LASP is
enabled to receive and respond to linking shadow protocols. The LASP does not recognize the TSA in this state.
For a target device in the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal
logic function of the device is performed. The instruction register is reset to an opcode that selects the optional
IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their
power-up values.
RUN-TEST/IDLE
In the stable Run-Test/Idle state, the LASP is enabled to receive and respond to linking shadow protocols. The
LASP does not recognize the TSA in this state. For a target device, Run-Test/Idle is a stable state in which the
test logic actively can be running a test or can be idle.
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