SN74LVT8986_07 Datasheet, PDF (10/54 Pages) Texas Instruments – 3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759E – OCTOBER 2002 – REVISED MAY 2007
www.ti.com
FUNCTION TABLE 3
(Secondary TAP Configuration Using Linking Shadow Protocol)
POSITION
Single
device
First device in
cascade
chain
Nor first and
not last
device in
cascade
chain
Last device in
cascade
chain
CONFI
G
BITS
2–0
HHH
HHL
HLH
HLL
LHH
LHL
LLH
LLL
HHH
HHL
HLH
HLL
LHH
LHL
LLH
LLL
HHH
HHL
HLH
HLL
LHH
LHL
LLH
LLL
HHH
HHL
HLH
HLL
LHH
LHL
LLH
LLL
STRST
2–0
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
STCK
2–0
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
PTCK
STMS2
STMS1
STMS0 STDO2 STDO1
STDO0
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
PTMS
PTMS
PTMS
PTMS
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
PTMS
PTMS
PTMS
PTMS
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
PTMS
PTMS
PTMS
PTMS
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
STMS2 ⁽¹⁾
PTMS
PTMS
PTMS
PTMS
STMS1 ⁽¹⁾
STMS1 ⁽¹⁾
PTMS
PTMS
STMS1 ⁽¹⁾
STMS1 ⁽¹⁾
PTMS
PTMS
STMS1 ⁽¹⁾
STMS1 ⁽¹⁾
PTMS
PTMS
STMS1 ⁽¹⁾
STMS1 ⁽¹⁾
PTMS
PTMS
STMS1 ⁽¹⁾
STMS1 ⁽¹⁾
PTMS
PTMS
STMS1 ⁽¹⁾
STMS1 ⁽¹⁾
PTMS
PTMS
STMS1 ⁽¹⁾
STMS1 ⁽¹⁾
PTMS
PTMS
STMS1 ⁽¹⁾
STMS1 ⁽¹⁾
PTMS
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
STMS0 ⁽¹⁾
PTMS
Z
Z
Z
Z
PTDI
STDI0
STDI1
STDI1
Z
Z
Z
Z
PTDI
STDI0
STDI1
STDI1
Z
Z
Z
Z
CTDI
STDI0
STDI1
STDI1
Z
Z
Z
Z
CTDI
STDI0
STDI1
STDI1
Z
Z
PTDI
STDI0
Z
Z
PTDI
STDI0
Z
Z
PTDI
STDI0
Z
Z
PTDI
STDI0
Z
Z
CTDI
STDI0
Z
Z
CTDI
STDI0
Z
Z
CTDI
STDI0
Z
Z
CTDI
STDI0
Z
PTDI
Z
PTDI
Z
PTDI
Z
PTDI
Z
PTDI
Z
PTDI
Z
PTDI
Z
PTDI
Z
CTDI
Z
CTDI
Z
PTDI
Z
PTDI
Z
CTDI
Z
CTDI
Z
PTDI
Z
PTDI
PTDO
Z
STDI0
STDI1
STDI1
STDI2
STDI2
STDI2
STDI2
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
STDI0
STDI1
STDI1
STDI2
STDI2
STDI2
STDI2
CTDO
CON2 CON1 CON0
CTDI
H
H
H
STDI0
H
H
L
STDI1
H
L
H
STDI1
H
L
L
STDI2
L
H
H
STDI2
L
H
L
STDI2
L
L
H
STDI2
L
L
L
CTDI
H
H
H
STDI0
H
H
L
STDI1
H
L
H
STDI1
H
L
L
STDI2
L
H
H
STDI2
L
H
L
STDI2
L
L
H
STDI2
L
L
L
CTDI
H
H
H
STDI0
H
H
L
STDI1
H
L
H
STDI1
H
L
L
STDI2
L
H
H
STDI2
L
H
L
STDI2
L
L
H
STDI2
L
L
L
CTDI
H
H
H
STDI0
H
H
L
STDI1
H
L
H
STDI1
H
L
L
STDI2
L
H
H
STDI2
L
H
L
STDI2
L
L
H
STDI2
L
L
L
(1) STMS level before steady-state conditions were established
In order to provide the ability to cascade multiple LASPs, pad bits are used to reduce propagation delays that
reduce the allowable test clock speed. These pad bits are located along the internal scan path of the LASP and,
therefore, must be accommodated in the boundary-scan test program. The number of these bits ranges from
one to four. The number and location completely depends on the configuration of the LASP. In Function Table 4,
each LASP relative position and configuration scan path uses a (1) to indicate a pad bit in the path.
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