PCI1225 Datasheet, PDF (20/131 Pages) Texas Instruments – PC CARD CONTROLLERS

PCI1225 GHK/PDV
PC CARD CONTROLLERS
SCPS035B – MAY 1998 – REVISED – MAY 2000
Terminal Functions (Continued)
CardBus PC Card address and data (slots A and B)
NAME
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
CC/BE3
CC/BE2
CC/BE1
CC/BE0
TERMINAL
PIN NUMBER
SLOT A†
SLOT B‡
PDV GHK PDV GHK
147 F19 81 W11
145 G17 79 R10
144 G18 78 U10
142 H15 77 V10
141 H14 76 W10
133 J19 67 R8
132 K14 66 W7
131 K15 65 V7
128 K19 62 W6
126 L15 60 V6
125 L17 59 U6
123 L19 57 V5
121 M18 55 R6
119 M15 54 U5
118 N19 53 W4
103 U15 37 M6
101 V15 35 M2
102 R14 36 M3
99 W15 33
L5
100 P14 34 M1
98 U14 32
L6
97 R13 30
L2
95 W14 29
L1
93 U13 27 K5
92 V13 26 K3
89 P12 23
J6
90 R12 24 K1
87 V12 20
J2
88 U12 21
J3
84 P11 18 H1
85 R11 19
J1
83 U11 17 H2
130 K17 63 P8
117 N18 52
T1
104 W16 39 N1
94 P13 28 K6
I/O
TYPE
FUNCTION
PC Card address and data. These signals make up the multiplexed CardBus address
I/O
and data bus on the CardBus interface. During the address phase of a CardBus cycle,
CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle,
CAD31–CAD0 contain data. CAD31 is the most-significant bit.
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the
same CardBus terminals. During the address phase of a CardBus cycle,
CC/BE3–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is
I/O used as byte enables. The byte enables determine which byte paths of the full 32-bit data
bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies
to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD8), and CC/BE3
applies to byte 3 (CAD31–CAD24).
CardBus parity. In all CardBus read and write cycles, the PCI1225 calculates even parity
across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1225
CPAR
106 R17 41
N3
I/O outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated
parity is compared to the initiator parity indicator; a compare error results in a parity error
assertion.
† _{Terminal name for slot A is preceded with A_. For example, the full name for terminals 106 and R17 is A_CPAR.}
‡ _{Terminal name for slot B is preceded with B_. For example, the full name for terminals 41 and N3 is B_CPAR.}
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