PCI1225 Datasheet, PDF (13/131 Pages) Texas Instruments – PC CARD CONTROLLERS

PCI1225 GHK/PDV
PC CARD CONTROLLERS
Terminal Functions (Continued)
SCPS035B – MAY 1998 – REVISED – MAY 2000
PCI address and data
TERMINAL
NUMBER
NAME
PDV GHK
I/O
TYPE
FUNCTION
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
170 A13
171 E12
173 B12
174 A12
176 B11
177 C11
165 E13
179 F11
183 E10
184 F10
185 A9
186 B9
188 F9
189 E9
190 A8
191 B8
204 F6
205 B5
206 E6
208 A4
172 C12
2
E3
3
F5
4
G6
6
E1
8
F2
9
G5
10
F1
11
H6
12 G3
14 G1
15 H5
C/BE3 162 A15
C/BE2 192 C8
C/BE1 203 A5
C/BE0 5
E2
PAR
202 C6
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
I/O interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other
destination information. During the data phase, AD31–AD0 contain data.
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command. During the data
I/O phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit
data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8),
C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).
PCI bus parity. In all PCI bus read and write cycles, the PCI1225 calculates even parity across the
I/O
AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI1225 outputs this parity
indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the
initiator parity indicator. A compare error results in the assertion of a parity error (PERR).
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