PCI1225 Datasheet, PDF (125/131 Pages) Texas Instruments – PC CARD CONTROLLERS

PCI1225 GHK/PDV
PC CARD CONTROLLERS
SCPS035B – MAY 1998 – REVISED – MAY 2000
PC Card cycle timing
The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and
I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address
setup and hold times, and the PC Card command active (low) interval. This allows the cycle generator to output
PC Card cycles that are as close to the Intel 82365SL-DF timing as possible, while always slightly exceeding
the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput.
The PC Card address setup and hold times are a function of the wait-state bits. Table 69 shows address setup
time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 70 and Table 71 show command active
time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 72 shows address hold time in PCLK
cycles and nanoseconds for I/O and memory cycles.
Table 69. PC Card Address Setup Time, t_su(A), 8-Bit and 16-Bit PCI Cycles
WAIT-STATE BITS
I/O
Memory WS1 0
Memory WS1 1
TS1 – 0 = 01
(PCLK/ns)
3/90
2/60
4/120
Table 70. PC Card Command Active Time, t_c(A), 8-Bit PCI Cycles
WAIT-STATE BITS
WS ZWS
0
0
I/O
1
X
0
1
00
0
01
X
Memory
10
X
11
X
00
1
TS1 – 0 = 01
(PCLK/ns)
19/570
23/690
7/210
19/570
23/690
23/690
23/690
7/210
Table 71. PC Card Command Active Time, t_c(A), 16-Bit PCI Cycles
WAIT-STATE BITS
WS ZWS
0
0
I/O
1
X
0
1
00
0
01
X
Memory
10
X
11
X
00
1
TS1 – 0 = 01
(PCLK/ns)
7/210
11/330
N/A
9/270
13/390
17/510
23/630
5/150
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