GC3021A Datasheet, PDF (20/38 Pages) Texas Instruments – 3.3V MIXER AND CARRIER REMOVAL CHIP

GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP
SLWS137A
The suggested default value for SYNC_REG1 is 7DF7 (HEX) which is to always sync AB_SYNC,
FREQ_SYNC and DITHER_SYNC (turns dithering off) and to sync PLL_SYNC and NCO_SYNC with the
oneshot strobe.
ADDRESS 2:
SYNC_REG1
BIT
TYPE
0-2 (LSBs) R/W
3-5
R/W
6-8
R/W
9-11
R/W
12-14
R/W
15 (MSB) R/W
NAME
AB_SYNC
PLL_SYNC
FREQ_SYNC
NCO_SYNC
DITHER_SYNC
-
DESCRIPTION
The PLL circuit accepts new A and B values when the
sync is asserted.
The PLL accumulator is cleared by this sync.
The PLL accepts the new FREQ value from the FREQ
registers when this sync is asserted.
The NCO accumulator is cleared by this sync.
The dither value circuit is cleared by this sync.
unused
4.3 DELAY CONTROL REGISTER
The DSA and DSB syncs are generated by delaying the SA and SB sync inputs by (2+DELAY)
clocks where DELAY ranges from 0 to 255. The suggested default is zero.
ADDRESS 3:
DELAY_REG
BIT
TYPE
0-7 (LSBs) R/W
8-15 (MSBs) R/W
NAME
DELAY_A
DELAY_B
DESCRIPTION
The DELAY value for DSA.
The DELAY value for DSB.
4.4 COUNTER CONTROL REGISTER
The internal counter counts in cycles of 16*(COUNT+1) clocks by counting down from
(16*COUNT+15) to zero and starting over again. The counter emits a terminal count (TC) each time it
reaches zero. The suggested default is 00FF (HEX) which sets a counter cycle of 4096.
ADDRESS 4:
COUNT_REG
BIT
0-15
TYPE
R/W
NAME
COUNT
DESCRIPTION
The counter period is 16*(COUNT+1) clocks.
Texas Instruments Incorporated
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