GC3021A Datasheet, PDF (19/38 Pages) Texas Instruments – 3.3V MIXER AND CARRIER REMOVAL CHIP

GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP
SLWS137A
4.2 SYNC CONTROL REGISTERS
Control registers SYNC_REG0 and SYNC_REG1 determine how the circuits within the chip are
synchronized. Each circuit which requires synchronization can be configured to be synchronized to the sync
inputs (SA and SB), to the delayed versions of these syncs (DSA and DSB), to the terminal count of the
internal counter (TC), or to the one-shot strobe (OS). The sync to each circuit can also be set to be always
on or always off. Each circuit is given a three bit sync mode control which is defined as:
Table 3: SYNC MODES
MODE
0
1
2
3
4
5
6
7
SYNC DESCRIPTION
“0” (never asserted)
SA
SB
DSA
DSB
TC
OS
“1” (always asserted)
NOTE: the internal syncs are active high. The SA and SB inputs have been inverted to be the active
high syncs SA and SB.
The suggested default setting for SYNC_REG0 is to sync everything to SA, value = 0249 (HEX).
ADDRESS 1:
SYNC_REG0
BIT
0-2 (LSBs)
3-5
6-8
9-11
12
13
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
14,15
R/W
NAME
COUNT_SYNC
OUTPUT_SYNC
OFFSET_SYNC
SNAP_SYNC
-
USE_CLK_EN
POWER_DOWN
DESCRIPTION
The counter sync selection
The selected sync is inverted and output on the SO pin.
The symbol offset sync.
The snapshot memory can be triggered by this sync.
unused
The clock enables CKENA and CKENB are ignored
when this bit is low.
These bits control the power down and keep alive circuit.
POWER_DOWN
MODE
0,1
Power down
2
Clock loss detect mode
3
Clock loss detect off
The USE_CLK_EN and POWER_DOWN bits initialize to zero upon power up. This puts the chip in
the power down mode to prevent a current surge if there is no clock provided. See Section 2.13 for details.
Texas Instruments Incorporated
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