BUF12840_12 Datasheet, PDF (20/26 Pages) Texas Instruments – Programmable Gamma-Voltage Generator with Integrated Two-Bank Memory and External EEPROM

BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
The BUF12840 acknowledges each byte. To
terminate communication, send a STOP or START
condition on the bus. Only DACs that have received
both bytes are updated.
Reading
To read the register of one DAC:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF12840 acknowledges this byte.
3. Send a DAC address byte. Bits D7−D5 are
unused and should be set to 0. Bits D4−D0 are
the DAC address; see Table 5. Only DAC
addresses 00000 to 01011 and 10000 to 11011
are valid and acknowledged.
4. Send a START or STOP/START condition on the
bus.
5. Send correct device address and read/write bit =
HIGH. The BUF12840 acknowledges this byte.
6. Receive two bytes of data. They are for the
specified DAC. The first received byte is the most
significant byte (bits D15−D8, of which only bits
D9 and D8 have meaning); the next is the least
significant byte (bits D7−D0).
7. Acknowledge after receiving each byte.
8. Send a STOP condition on the bus.
See Figure 22.
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Communication may be terminated by sending a
premature STOP or START condition on the bus, or
by not sending the acknowledge.
To read multiple DAC registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF12840 acknowledges this byte.
3. Send either the Register 0 address byte to start
at the first DAC or send the address byte for
whichever DAC is the first in the sequence of
DACs to be read. The BUF12840 begins with this
DAC and steps through subsequent DACs in
sequential order.
4. Send the device address and read/write bit =
HIGH.
5. Receive bytes of data. The first two bytes are for
the specified DAC. The first received byte is the
most significant byte (bits D15−D8, of which only
bits D9 and D8 have meaning). The next byte is
the least significant byte (bits D7−D0).
6. Acknowledge after receiving each byte.
7. When all desired DACs have been read, send a
STOP or START condition on the bus.
See Figure 23.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or
by not sending the acknowledge.
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