BUF12840_12 Datasheet, PDF (18/26 Pages) Texas Instruments – Programmable Gamma-Voltage Generator with Integrated Two-Bank Memory and External EEPROM

BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
READ/WRITE OPERATIONS
The BUF12840 is able to read from a single DAC or
multiple DACs, or write to the register of a single
DAC, or multiple DACs in a single communication
transaction. DAC addresses for BANK0 begin with
00000, which corresponds to Register 0, through
01011, which corresponds to Register 11. DAC
addresses for BANK1 begin with 10000, which
corresponds to Register 0, through 11011, which
corresponds to Register 11; see Table 5. Write
commands are performed by setting the read/write bit
LOW. Setting the read/write bit HIGH performs a read
transaction.
Writing
To write to a single DAC register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF12840 acknowledges this byte.
3. Send a DAC address byte. Bits D7−D5 are
unused and should be set to 0. Bits D4−D0 are
the DAC address; see Table 5. Only DAC
addresses 00000 to 01011 and 10000 to 11011
are valid and acknowledged.
4. Send two bytes of data for the specified DAC.
Begin by sending the most significant byte first
(bits D15−D8, of which only bits D9 and D8 are
used), followed by the least significant byte (bits
D7−D0). The DAC register is updated after
receiving the second byte.
5. Send a STOP condition on the bus.
See Figure 20.
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The BUF12840 acknowledges each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register is not updated. Updating the DAC register is
not the same as updating the DAC output voltage;
see the Output Latch section.
The process of updating multiple registers begins the
same as when updating a single register. However,
instead of sending a STOP condition after writing the
addressed register, the master continues to send
data for the next register. The BUF12840
automatically and sequentially steps through
subsequent registers as additional data are sent. The
process continues until all desired registers have
been updated or a STOP condition is sent.
To write to multiple registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF12840 acknowledges this byte.
3. Send either the Register 0 address byte to start
at the first DAC or send the address of whichever
DAC is the first to be updated. The BUF12840
begins with this DAC and steps through
subsequent DACs in sequential order.
4. Send the bytes of data. The first two bytes are for
the DAC addressed in step 3. Its register is
automatically updated after receiving the second
byte. The next two are for the following DAC. The
DAC register is updated after receiving the fourth
byte. The last two bytes are for Register 11. The
DAC register is updated after receiving the 24th
byte. For each DAC, begin by sending the most
significant byte (bits D15−D8, of which only bits
D9 and D8 have meaning), followed by the least
significant byte (bits D7−D0).
5. Send a STOP condition on the bus.
See Figure 21.
When the DAC registers are written through a
two-wire communication, changing the BKSEL pin
does not affect the communication because the
banks have different addresses. However, when
loading the DACs through an I²C communication, the
bank to be loaded is decided by the BKSEL pin.
Therefore, if the BKSEL pin is switched during a
two-wire load, the new value of BKSEL determines
the bank that is loaded.
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