BQ24130_15 Datasheet, PDF (20/29 Pages) Texas Instruments – 600-kHz Synchronous Switch-Mode Host-ControlledBattery/Supercapacitor Charger With 4-A Integrated MOSFETs

bq24130
SLUSAN2C – JULY 2011 – REVISED JUNE 2012
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A cost effective and small size solution is shown in Figure 18. The R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result the overvoltage spike is limited to a safe level. D1 is used
for reverse voltage protection for AVCC pin. C2 is AVCC pin decoupling capacitor and it should be place to
AVCC pin as close as possible. The R2 and C2 form a damping RC network to further protect the IC from high
dv/dt and high voltage spike. C2 value should be less than C1 value so R1 can dominant the equivalent ESR
value to get enough damping effect for hot plug-in. R1 and R2 package must be sized enough to handle inrush
current power loss according to resistor manufacturer’s data sheet. The filter components value always need to
be verified with real application and minor adjustments may need to fit in the real application circuit.
If the input is 5 V (USB host or USB adapter), the D1 can be saved. R2 has to be 5 Ω or higher to limit the
current if the input is reversely inserted.
D1
Adapter
Connector
R1 (2010)
2W
C1
2.2mF
R2 (1206)
4.7 - 30W
VCC pin
C2
0.1 - 1mF
Figure 18. Input Filter
PCB LAYOUT
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 19) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential
1. Place input capacitor as close as possible to PVCC supply and ground connections and use shortest copper
trace connection. These parts should be placed on the same layer of PCB instead of on different layers and
using vias to make this connection.
2. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 20 for Kelvin connection for
best current accuracy). Place decoupling capacitor on these traces next to the IC.
4. Place output capacitor next to the sensing resistor output and ground.
5. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
6. Route analog ground separately from power ground and use single ground connection to tie charger power
ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins
to reduce inductive and capacitive noise coupling. Use thermal pad as the single ground connection point to
connect analog ground and power ground together. Or using a 0 Ω resistor to tie analog ground to power
ground (thermal pad should tie to analog ground). A star-connection under thermal pad is highly
recommended.
7. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
8. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
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