BQ2085 Datasheet, PDF (20/56 Pages) Texas Instruments – SBS-COMPLIANT GAS GAUGE IC FOR USE WITH THE bq29311

bq2085
SLUS541 – OCTOBER 2002
Low-Power Modes
The bq2085 enters sleep mode when the charge and discharge current is less than the threshold programmed
in Sleep Current Threshold DF 0xe5, the SMBus lines are low for at least 2 s, and bit 4 of Misc. Configuration
DF 0x2a is set to zero. The bq2085 wakes up periodically to monitor voltage and temperature and to apply
self-discharge adjustment. The sleep period is set in Sleep Timer DF 0xe7. The bq2085 wakes up at a period
set by Sleep Current Time DF 0xe6 to measure current. The bq2085 comes out of sleep when the SMBus lines
go high or if the current is greater than Sleep Current Threshold. A rising edge on SMBC or SMBD restores the
bq2085 to the full operating mode.
Reset Conditions
On power-up the entire IC is reset and data is loaded from Data Flash to configure the SBS Data and the system.
On a partial reset (loss of VCC but RBI holds RAM valid) then a limited number of locations are taken.
These actions are the following:
D The AFE registers are rewritten.
D PackStatus() VDQ flag is cleared (the proposed change is not to clear VDQ).
D PackStatus() EDV2 flag is cleared.
D BatteryStatus() DISCHARGING flag is cleared.
D The charger and alarm broadcast period is set to 10 seconds between broadcasts.
COMMUNICATION
The bq2085 includes an SMBus communication port. The SMBus interface is a 2-wire bidirectional protocol
using the SMBC (clock) and SMBD (data) pins. The communication lines are isolated from VCC and may be
pulled-up higher than V_CC. Also, the bq2085 does not pull these lines low if V_CC to the part is zero.
The communication ports allow a host controller, an SMBus compatible device, or other processor to access
the memory registers of the bq2085. In this way a system can efficiently monitor and manage the battery.
SMBus
The SMBus interface is a command-based protocol. A processor acting as the bus master initiates
communication to the bq2085 by generating a start condition. A start condition consists of a high-to-low
transition of the SMBD line while the SMBC is high. The processor then sends the bq2085 device address of
0001011 (bits 7-1) plus a R/W bit (bit 0) followed by an SMBus command code. The R/W bit (LSB) and the
command code instruct the bq2085 to either store the forthcoming data to a register specified by the SMBus
command code or output the data from the specified register. The processor completes the access with a stop
condition. A stop condition consists of a low-to-high transition of the SMBD line while the SMBC is high. With
SMBus, the most-significant bit (MSB) of a data byte is transmitted first.
In some instances, the bq2085 acts as the bus master. This occurs when the bq2085 broadcasts charging
requirements and alarm conditions to device addresses 0x12 (SBS Smart Charger) and 0x10 (SBS Host
Controller.)
SMBus Protocol
The bq2085 supports the following SMBus protocols:
D Read word
D Write word
D Block read
A processor acting as the bus master uses the three protocols to communicate with the bq2085. The bq2085
acting as the bus master uses the write word protocol.
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