THS8134 Datasheet, PDF (2/24 Pages) Texas Instruments – TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION

THS8134, THS8134A, THS8134B
TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRI-LEVEL SYNC GENERATION
SLVS205D – MAY 1999 – REVISED MARCH 2000
description (continued)
Finally the input format can be either 3×8 bit 4:4:4, 2×8 bit 4:2:2, or 1×8 bit 4:2:2. This enables a direct interface
to a wide range of video DSP/ASICs including parts generating ITU-BT.656 formatted output data.
AVAILABLE OPTIONS
PACKAGE
TA
TQFP-48 PowerPAD
THS8134CPHP†
0°C to 70°C
THS8134ACPHP‡
THS8134BCPHP‡
† _{In the THS8134CPHP, the KIMBALmaximum specification is}
assured over full temperature range and the KIMBAL(SYNC)
maximum specification is assured at 25°C. The position of
the blanking level is as shown in Table 1.
‡ _{In the THS8134ACPHP and the THS8134BCPHP, both the}
KIMBALmaximum specification and the KIMBAL(SYNC)
maximum specification are assured over the full temperature
range. The position of the blanking level is as shown in
Table 1.
Terminal Functions
TERMINAL
I/O
NAME
PIN
DESCRIPTION
ABPb
AGY
45 O Analog red, green and blue respectively Pr, Y and Pb current outputs, capable of directly driving a doubly
41
O ^{terminated 75-Ω coaxial cable.}
ARPr
43 O
AVDD
AVSS
BLANK
40,44
42,46
23
I Analog power supply (5 V ±10%). All AVDD terminals must be connected.
I Analog ground
I Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the ARPr, AGY and
ABPb outputs are driven to the blanking level, irrespective of the value on the data inputs. SYNC takes
precedence over BLANK, so asserting SYNC (low) while BLANK is active (low) will result in sync generation.
BPb0–BPb7 8–1
I Blue or Pb pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for
different operating modes.
CLK
26
I Clock input. A rising edge on CLK latches RPr0-7, GY0-7, BPb0-7, BLANK, SYNC, and SYNC_T. The M2 input is
latched by a rising edge on CLK also, but only when additional conditions are satisfied, as explained in its
terminal description.
COMP
DVDD
DVSS
FSADJ
39
O Compensation terminal. A 0.1 µF capacitor must be connected between COMP and AVDD.
12
I Digital power supply (3-V to 5-V range)
11
I Digital ground
38
I Full-scale adjust control. The full-scale current drive on each of the output channels is determined by the value of
a resistor RFS connected between this terminal and AVSS. The nominal value of RFS is 430 Ω, corresponding to
26.67 mA full-scale current. The relationship between RFS and the full-scale current level for each operation
mode is explained in the functional description.
GY0–GY7
34–27 I Green or Y pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for
different operating modes.
M1
47
I Operation mode control 1. M1 is directly interpreted by the device (it is not latched by CLK). M1 configures device
according to Table 1.
2
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