THS8134 Datasheet, PDF (12/24 Pages) Texas Instruments – TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION

THS8134, THS8134A, THS8134B
TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRI-LEVEL SYNC GENERATION
SLVS205D – MAY 1999 – REVISED MARCH 2000
electrical characteristics over recommended operating conditions with f_CLK = 80 MSPS and use
of internal reference voltage V_ref, with R_(FS) = R_(FSnom) (unless otherwise noted) (continued)
digital inputs – dc characteristics
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
IIH
IIL
IIL(CLK)
IIH(CLK)
High-level input current
Low-level input current
Low-level input current, CLK
High-level input current, CLK
AVDD = DVDD = 5 V
–1
Digital inputs and CLK at 0 V for IIL;
Digital inputs and CLK at 5 V for IIH
–1
1 µA
µA
1 µA
CI
Input capacitance
TA = 25°C
7
pF
ts
Data and control inputs setup time
3
ns
tH
Data and control inputs hold time
0
ns
RGB and YPbPr 4:4:4
7
td(D)
Digital process delay from first registered color
component of pixel† (see Figures 3–5)
YPbPr 4:2:2 2×8 bit
YPbPr 4:2:2 1×8 bit
8
CLK
periods
9
† _{This parameter is assured by design and not production tested. The digital process delay is defined as the number of CLK cycles required for}
the first registered color component of a pixel, starting from the time of registering it on the input bus, to propagate through all processing and
appear at the DAC output drivers. The remaining delay through the IC is the analog delay td(A) of the analog output drivers.
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