THS1050IPHP Datasheet, PDF (2/21 Pages) Texas Instruments – 10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS

THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
functional block diagram
AVDD DVDD DRVDD
VIN+
Buffer
Stage 1
Stages 2 – 9
Stage 10
900 Ω
S/H
VIN–
Σ
Σ ^A/D
VREFIN+
VREFOUT+
VREFOUT–
VREFIN–
VCM
CLK+
CLK–
A/D D/A
3.0 V
1
Reference
2.0 V ^AVDD/2
Timing
A/D D/A
1
1
Digital Error Correction
AVSS DVSS DRVSS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
AVDD
2, 5, 12 43,
45, 47
I Analog power supply
AVSS
1, 11, 13, 41, I Analog ground return for internal analog circuitry
42, 44, 46
CLK+
15
I Clock input
CLK–
16
I Complementary clock input
D9–D0
25–34
O Digital data output bits; LSB= D0, MSB = D9 (2s complement output format)
DRVDD
DRVSS
DVDD
DVSS
VBG
VCM
VIN+
VIN_–
VREFIN _–
VREFIN+
VREFOUT+
VREFOUT _–
24, 37, 38
23, 39, 40
17, 20, 22
18, 19, 21
10
48
3
4
7
8
9
6
I Digital output driver supply
I Digital output driver ground return
I Positive digital supply
I Digital ground return
O Band gap reference. Bypass to ground with a 1-µF and a 0.01-µF chip capacitor.
O Common mode voltage output. Bypass to ground with a 0.1-µF and a 0.01-µF chip device capacitor.
I Analog signal input
I Complementary analog signal input
I External reference input low
I External reference input high
O Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.
O Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.
2
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265