THS1050IPHP Datasheet, PDF (15/21 Pages) Texas Instruments – 10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS

ac Signal Source
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
APPLICATION INFORMATION
3 V p-p
to
5 V p-p
Zo
R = Zo
Impedance Ratio = 1:4
0.1 µF
CLK+
T4-1H
R = 4 Zo _THS1050
CLK–
VCM
0.01 µF
0.1 µF
Figure 20. Driving the Clock From an Impedance Matched Source
The clock signals, CLK+ and CLK–, should be well matched and must both be driven.
A transformer ensures minimal skew between the two complementary channels. However, skew levels of up
to 500 ps between CLK+ and CLK– can be tolerated with some performance degradation.
The clock input can also be driven differentially with a 5-V TTL signal by using an RF transformer to convert the
TTL signal to a differential signal. The TTL signal is ac-coupled to the positive primary terminal with a high pass
circuit. The negative terminal of the transformer is connected to ground (see Figure 21). The transformer
secondary is connected to the CLK inputs.
5 V TTL CLK
Impedance Ratio = 1:4
0.1 µF
CLK+
T4 - 1H
THS1050
CLK–
VCM
0.01 µF
Figure 21. TTL Clock Input
0.1 µF
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