SN74AVC16646 Datasheet, PDF (2/18 Pages) Texas Instruments – 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

SN74AVC16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES181F – DECEMBER 1998 – REVISED JUNE 2005
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DESCRIPTION (CONTINUED)
The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the
transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the
isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function still is enabled and may be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16646 is characterized for operation from –40°C to 85°C.
TERMINAL ASSIGNMENTS
DGG OR DGV PACKAGE
(TOP VIEW)
1DIR 1
1CLKAB 2
1SAB 3
GND 4
1A1 5
1A2 6
V_CC 7
1A3 8
1A4 9
1A5 10
GND 11
1A6 12
1A7 13
1A8 14
2A1 15
2A2 16
2A3 17
GND 18
2A4 19
2A5 20
2A6 21
V_CC 22
2A7 23
2A8 24
GND 25
2SAB 26
2CLKAB 27
2DIR 28
56 1OE
55 1CLKBA
54 1SBA
53 GND
52 1B1
51 1B2
50 V_CC
49 1B3
48 1B4
47 1B5
46 GND
45 1B6
44 1B7
43 1B8
42 2B1
41 2B2
40 2B3
39 GND
38 2B4
37 2B5
36 2B6
35 V_CC
34 2B7
33 2B8
32 GND
31 2SBA
30 2CLKBA
29 2OE
2