CD74HC166 Datasheet, PDF (2/13 Pages) Texas Instruments – High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register

CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
Functional Diagram
D0 D1 D2 D3 D4 D5 D6 D7
PE
PARALLEL ENABLE CIRCUIT
D0
D7
D_S
8 - REGISTERS
Q7
CP
CE
MR
TRUTH TABLE
INPUTS
MASTER
RESET
PARALLEL
ENABLE
CLOCK
ENABLE
CLOCK
SERIAL
PARALLEL
D0 D7
INTERNAL
Q STATES
Q0
Q1
OUTPUT
Q7
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
Q00
Q10
Q0
H
L
L
↑
X
a...h
a
b
h
H
H
L
↑
H
X
H
Q0n
Q6n
H
H
L
↑
L
X
L
Q0n
Q6n
H
X
H
↑
X
X
Q00
Q10
Q70
H= High Voltage Level
L= Low Voltage Level
X= Don’t Care
↑= Transition from Low to High Level
a...h = The level of steady-state input at inputs D0 thru D7, respectively.
Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established.
Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ↑ transition of the clock.
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