CD74HC166 Datasheet, PDF (1/13 Pages) Texas Instruments – High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register

Data sheet acquired from Harris Semiconductor
SCHS157C
February 1998 - Revised October 2003
CD54HC166, CD74HC166,
CD54HCT166, CD74HCT166
High-Speed CMOS Logic
8-Bit Parallel-In/Serial-Out Shift Register
[ /Title
(CD74
HC166
,
CD74
HCT16
6)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Bit
Paral-
lel-
In/Seri
Features
Description
• Buffered Inputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
Pinout
CD54HC166, CD54HCT166
(CERDIP)
CD74HC166, CD74HCT166
(PDIP, SOIC)
TOP VIEW
DS 1
D0 2
D1 3
D2 4
D3 5
CE 6
CP 7
GND 8
16 V_CC
15 PE
14 D7
13 Q7
12 D6
11 D5
10 D4
9 MR
The ’HC166 and ’HCT166 8-bit shift register is fabricated
with silicon gate CMOS technology. It possesses the low
power consumption of standard CMOS integrated circuits,
and can operate at speeds comparable to the equivalent low
power Schottky device.
The ’HCT166 is functionally and pin compatible with the
standard ’LS166.
The 166 is an 8-bit shift register that has fully synchronous
serial or parallel data entry selected by an active LOW Parallel
Enable (PE) input. When the PE is LOW one setup time before
the LOW-to-HIGH clock transition, parallel data is entered into
the register. When PE is HIGH, data is entered into the internal
bit position Q0 from Serial Data Input (DS), and the remaining
bits are shifted one place to the right (Q0 → Q1 → Q2, etc.)
with each positive-going clock transition. For expansion of the
register in parallel to serial converters, the Q7 output is con-
nected to the DS input of the succeeding stage.
The clock input is a gated OR structure which allows one
input to be used as an active LOW Clock Enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary and
can be reversed for layout convenience. The LOW-to-HIGH
transition of CE input should only take place while the CP is
HIGH for predictable operation.
A LOW on the Master Reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all bit
positions to a LOW state.
Ordering Information
PART NUMBER
TEMP. RANGE (^oC)
PACKAGE
CD54HC166F3A
-55 to 125
16 Ld CERDIP
CD54HCT166F3A
-55 to 125
16 Ld CERDIP
CD74HC166E
-55 to 125
16 Ld PDIP
CD74HC166M
-55 to 125
16 Ld SOIC
CD74HC166MT
-55 to 125
16 Ld SOIC
CD74HC166M96
-55 to 125
16 Ld SOIC
CD74HCT166E
-55 to 125
16 Ld PDIP
CD74HCT166M
-55 to 125
16 Ld SOIC
CD74HCT166MT
-55 to 125
16 Ld SOIC
CD74HCT166M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1