BQ29200 Datasheet, PDF (2/15 Pages) Texas Instruments – Voltage Protection with Automatic Cell Balance for 2-Series Cell Li-Ion Batteries

bq29200
bq29209
SLUSA52 – JUNE 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
T_A
PART NUMBER
–40°C to
+110°C
BQ29200
BQ29209
OUT PIN
LATCH
OPTION
No
No
ORDERING INFORMATION
PACKAGE
PACKAGE
PACKAGE
DESIGNATOR MARKING
OVP
QFN-8
DRB
200
4.35 V
209
4.30 V
ORDERING INFORMATION
TAPE AND REEL
(LARGE)
TAPE AND REEL
(SMALL)
BQ29200DRBR
BQ29209DRBT
BQ29209DRBR
BQ29209DRBT
THERMAL INFORMATION
q_JA
q_JC(top)
q_JB
y_JT
y_JB
q_JC(bottom)
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance ⁽³⁾
Junction-to-board thermal resistance ⁽⁴⁾
Junction-to-top characterization parameter ⁽⁵⁾
Junction-to-board characterization parameter ⁽⁶⁾
Junction-to-case(bottom) thermal resistance ⁽⁷⁾
bq2920x
DRB
8 PINS
50.5
25.1
19.3
0.7
18.9
5.2
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
PIN NAME
CB_EN
CD
GND
OUT
VC1
VC1_CB
VC2
VDD
PIN FUNCTIONS
NO.
DESCRIPTION
6
Cell balance enable
4
Connection to external capacitor for programmable delay time
5
Ground pin
8
Output
2
Sense voltage input for bottom cell
3
Cell balance input for bottom cell
1
Sense voltage input for top cell
7
Power supply
2
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