TMS320DM368 Datasheet, PDF (195/208 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM368
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6.23.4 HPI Electrical Data/Timing
SPRS668A – APRIL 2010
Table 6-99. Timing Requirements for Host-Port Interface Cycles^{(1) (2)} (see Figure 6-65 and Figure 6-66)
NO.
1
t_{su(SELV-HSTBL)}
2
t_{h(HSTBL-SELV)}
3
t_w(HSTBL)
4
t_w(HSTBH)
11
t_{su(HDV-HSTBH)}
12
t_h(HSTBH-HDV)
13
t_{h(HRDYL-HSTBL)}
Setup time, select signals⁽³⁾ valid before HSTROBE low
Hold time, select signals⁽³⁾ valid after HSTROBE low
Pulse duration, HSTROBE active low
Pulse duration, HSTROBE inactive high between consecutive accesses
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE high after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
DEVICE
MIN
6
2
15
2P
5
2
MAX
UNIT
ns
ns
ns
ns
ns
ns
2
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3 , Device Clocking
(3) Select signals include: HCNTLA, HCNTLB, HR/W and HHWIL.
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 195
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