TMS320DM368 Datasheet, PDF (145/208 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM368
www.ti.com
SPRS668A – APRIL 2010
Table 6-54. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to VCLK^{(1) (2) (3)}(see Figure 6-38)
NO.
PARAMETER
DEVICE
UNIT
MIN
MAX
17
t_c(VCLK)
Cycle time, VCLK
18
t_w(VCLKH)
Pulse duration, VCLK high
19
t_w(VCLKL)
Pulse duration, VCLK low
20
t_t(VCLK)
Transition time, VCLK
21 t_{d(VCLKINH-VCLKH)} Delay time, VCLKIN high to VCLK high
22 t_{d(VCLKINL-VCLKL)} Delay time, VCLKIN low to VCLK low
23
t_{d(VCLK-VCTLV)}
Delay time, VCLK edge to VCTL valid
24
t_{d(VCLK-VCTLIV)}
Delay time, VCLK edge to VCTL invalid
25
t_{d(VCLK-VDATAV)}
Delay time, VCLK edge to VDATA valid
26
t_{d(VCLK-VDATAIV)}
Delay time, VCLK edge to VDATA invalid
13.33
5.7
5.7
3
3
-1.5
-1.5
160 ns
ns
ns
3 ns
16 ns
16 ns
1.5 ns
ns
1.5 ns
ns
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.
(2) VCLKIN = PCLK or EXTCLK. Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking. For
timing specifications relating to PCLK, see Table 6-44 , Timing Requirements for VPFE PCLK Master/Slave Mode.
(3) VCTL= HSYNC, VSYNC, FIELD and LCD_OE.
VCLKIN ^(A)
21
22
VCLK
(Positive Edge
Clocking)
VCLK
(Negative Edge
Cl oc k i ng )
VCTL^(B)
VDATA^(C)
17
23
25
19
18
24
20
20
26
A. VCLKIN = PCLK or EXTCLK. Note Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking.
B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE
C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]
Figure 6-38. VPBE Control and Data Output Timing With Respect to VCLK
6.12.2.4 High-Definition (HD) DACs and Video Buffer Electrical Data/Timing
Three DACs and a video buffer are available on the device.
6.12.2.4.1 HD DACs-Only Option
In the HD DACs-only configuration, the internal video buffer is not used and an external video buffer is
attached to the DACs. Another solution is to use a Video Amplifier, such as the Texas Instruments'
THS7303 which provides a complete solution to the typical output circuit shown in Figure 6-39.
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 145
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