TMS320DM6441_10 Datasheet, PDF (193/232 Pages) Texas Instruments – Digital Media System-on-Chip

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SPIx_CLK
(Clock Polarity = 0)
TMS320DM6441
Digital Media System-on-Chip
SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008
1
2
3
SPIx_CLK
(Clock Polarity = 1)
Figure 7-59. SPI_CLK Timing
7.16.2.1 SPI Master Mode Timings (Clock Phase = 0)
Table 7-76. Timing Requirements for SPI Master Mode [Clock Phase = 0] ⁽¹⁾(see Figure 7-60)
NO.
4 t_su(DIV-CLKL)
Setup time, SPI_DI (input) valid before SPI_CLK (output)
falling edge
Clock Polarity = 0
5
t_su(DIV-CLKH)
Setup time, SPI_DI (in put) valid before SPI_CLK (output)
rising edge
Clock Polarity = 1
6 t_h(CLKL-DIV)
Hold time, SPI_DI (input) valid after SPI_CLK (output) falling
edge
Clock Polarity = 0
7 t_h(CLKH-DIV)
Hold time, SPI_DI (input) valid after SPI_CLK (output) rising
edge
Clock Polarity = 1
1.05 V and 1.2 V
UNIT
MIN
MAX
0.5P + 9.4
ns
0.5P + 9.4
ns
0.5P - 4.5
ns
0.5P - 4.5
ns
(1) P = Period of the SPI module clock in nanoseconds (SYSCLK5).
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Peripheral and Electrical Specifications 193