TMS320DM6441_10 Datasheet, PDF (145/232 Pages) Texas Instruments – Digital Media System-on-Chip

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7.11.2.2 ATA/CF Multiword DMA Timing
TMS320DM6441
Digital Media System-on-Chip
SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008
Table 7-40. Timings for ATA/CF Module — Multiword DMA AC Timing⁽¹⁾⁽²⁾ (see Figure 7-27)
NO.
1 t₀
2 t_D
3 t_E
4 t_F
5 t_G
6 t_H
7 t_I
8 t_J
9 t_KR
10 t_KW
11 t_LR
12 t_LW
13 t_M
14 t_N
15 t_Z
Cycle time
DIOW/DIOR active low pulse duration
DIOR data access, DIOR falling edge to DD[15:0]
valid
DIOR data hold time, DD[15:0] valid after DIOR
rising edge
DIOW/DIOR data setup time, DD[15:0] (OUT) valid
before DIOW/DIOR rising edge
DIOW/DIOR data setup time, DD[15:0] (IN) valid
before DIOW/DIOR rising edge
DIOW data hold time, DD[15:0] valid after DIOW
rising edge
DMACK to DIOW/DIOR setup
DIOW/DIOR to DMACK hold
DIOR negated pulse width
DIOW negated pulse width
DIOR to DMARQ delay
DIOW to DMARQ delay
ATA_CSx valid to DIOW/DIOR setup
ATA_CSx valid after DIOW/DIOR rising edge hold
DMACK to read data (DD[15:0]) released
MODE
0-2
0-2
0
1
2
0-2
0-2
0
1
2
0-2
0-2
0-2
0-2
0-2
0
1
2
0-1
2
0-2
0-2
0
1-2
1.05 V and 1.2 V
MIN
(DMASTB + DMARCVR + 2)P - 0.5
(DMASTB + 1)P - 1
5
(DMASTB)P
100
30
20
(HWNHLD + 1)P + 1
(DMARCVR + 1)P - 1.7
5P - 5.9
(DMARCVR + 1)P - 1
(DMARCVR + 1)P - 1
(DATRCVR)P - 1.7
5P - 1.7
MAX
150
60
50
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120 ns
45 ns
35 ns
40 ns
35 ns
ns
ns
20 ns
25 ns
(1) P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 405 MHz, use P = 14.8 ns.
(2) DMASTB equals the value programmed in the DMASTBxP bit field in the DMASTB register. DMARCVR equals the value programmed
in the DMARCVRxP bit field in the DMARCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the
MISCCTL register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number
SPRUE21).
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Peripheral and Electrical Specifications 145