TLC5952 Datasheet, PDF (19/33 Pages) Texas Instruments – 24-Channel, Constant-Current LED Driver with Global Brightness Control and LED Open-Short Detection

TLC5952
www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009
REGISTER AND DATA LATCH CONFIGURATION
The TLC5952 has two writable data latches: the output on/off data latch and the control data latch. Both data
latches are 24 bits in length. If the common shift register MSB is '0', the least significant 24 bits of data from the
25-bit common shift register are latched into the output on/off data latch. If the MSB is '1', the data are latched
into the control data latch. Figure 33 shows the common shift register and the control data latch configuration.
SOUT
Common Shift Register (25 Bits)
MSB
24
23
22
21
20
19
LSB
5
4
3
2
1
0
Latch Common Common Common Common Common
Common Common Common Common Common Common
Select Data
Data
Data
Data
Data
¼
Data
Data
Data
Data
Data
Data
Bit
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIN
SCK
24
Output On/Off Data Latch (24 Bits)
MSB
23
22
21
20
19
OUTB7 OUTG7 OUTR7 OUTB6 OUTG6
On
On
On
On
On
24
LSB
5
4
3
2
1
0
OUTB1 OUTG1 OUTR1 OUTB0 OUTG0 OUTR0
¼
On
On
On
On
On
On
24
To Output On/Off Control Circuit
24
Control Data Latch (24 Bits)
MSB
23
22
21
20
14
13
LSB
7
6
0
Detection Detection Detection OUTB0-7
OUTB0-7 OUTG0-7
OUTG0-7 OUTR0-7
OUTR0-7
Voltage Voltage Voltage Bright
¼
Bright Bright
¼
Bright Bright
¼
Bright
Select 2 Select 1 Select 0 Bit 6
Bit 0
Bit 6
Bit 0
Bit 6
Bit 0
The latch pulse comes
from LAT when the
MSB of the common
shift register is ‘0’.
The latch pulse comes
from LAT when the
MSB of the common
shift register is ‘1’.
3
7
7
7
To LSD/LOD
Circuit
To Global Brightness
Control Circuit
for OUTB0-OUTB7
To Global Brightness
Control Circuit
for OUTG0-OUTG7
To Global Brightness
Control Circuit
for OUTR0-OUTR7
Figure 33. Grayscale Shift Register and Data Latch Configuration
Output On/Off Data Latch
The output on/off data latch is 24 bits long. This latch is used to turn each output current sink (OUTRn/Gn/Bn) on
or off. When the MSB of the common shift register is set to '0', the lower 24 bits are written to the output on/off
data latch on the rising edge of LAT. If the output on/off data latch bit corresponding to an output is '0', the output
is turned off; if the bit is a '1', the output is turned on.
When the IC is powered on, the data in the output on/off data latch are not set to any default value. Therefore,
the on/off control data should be written to the data latch before the constant-current outputs are turned on.
Copyright © 2009, Texas Instruments Incorporated
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