TLC5942 Datasheet, PDF (19/33 Pages) Texas Instruments – 16-Channel, 12-Bit PWM LED Driver with 7-Bit Dot Correction

TLC5942
www.ti.com
SBVS096B – OCTOBER 2007 – REVISED OCTOBER 2007
Grayscale Shift Register and Data Latch
The Grayscale (GS) Shift Registers and data latches are each 192 bits in length, and are used to set the PWM
timing for each constant current driver. See Table 3 for the ON time duty of each GS data bit. Figure 22 shows
the shift register and latch configuration. Refer to Figure 9 for the timing diagram for writing data into the GS shift
register and latch. The driver on time is set by the data in the GS data latch. GS data present on the GSSIN pin
are clocked into the GS Shift Register with each rising edge of the GSSCLK pin. Data are shifted in MSB first.
Data are latched from the shift register into the GS data latch with a rising edge on the XGSLAT pin.
When the IC is powered on, the data in Grayscale Shift Register and data latch are not set to any default value.
Therefore, grayscale data must be written to the GS latch before turning on the constant current output. Also,
BLANK should be high when powered on because the constant current may also turn on. All constant current
outputs are off when BLANK is high.
The Status Information Data (SID) byte is overwritten on the most significant 17 bits of the Grayscale Shift
Register at the rising edge of the first GSSCLK after XGSLAT goes low.
Grayscale Shift Register (12 Bits 16 Channels)
´
GSSOUT
GS Data for OUT15
MSB
191
180
¼ GS Data for OUT14 GS Data for OUT1
179
175
7
OUT15-Bit11
¼
(LOD-OUT15)
OUT15-Bit0 OUT14-Bit11
¼
(LOD-OUT4) (LOD-OUT3)
OUT14-Bit7
¼
(TEF)
OUT1-Bit0
GS Data for OUT0
LSB
6
0
¼ _OUT0-Bit11
OUT0-Bit0
GSSIN
GSSCLK
SID Data are Overwritten Between Bits 191 and 175
¼
¼
¼
¼
GS Data for OUT15
MSB
191
180
¼ GS Data for OUT14 GS Data for OUT1
179
12
GS Data for OUT0
LSB
11
0
¼ ¼ ¼ ¼ _OUT15-Bit11
OUT15-Bit0 OUT14-Bit11
OUT14-Bit7
OUT1-Bit0 OUT0-Bit11
OUT0-Bit0
XGSLAT
Grayscale Data Latch (12 Bits 16 Channels)
´
192 Bits
To PWM Timing Control Block
Figure 22. Grayscale Shift Register and Data Latch Configuration
Dot Correction Shift Register and Data Latch
The Dot Correction (DC) Shift Registers and latches are each 112 bits in length and are used to individually
adjust the constant current values for each constant current driver. Each channel can be adjusted from 0% to
100% of the maximum LED current with 7-bit resolution. Table 2 describes the percentage of the maximum
current for each dot correction data. See Figure 23 for the Dot Correction Shift Register and data latch
configuration. Figure 10 illustrates the timing chart for writing data into the DC Shift Registers and latches. Each
channel LED current is dot-corrected by the percentage corresponding to the data in its DC data latch. DC data
present on the DCSIN pin are clocked into the DC Shift Register with each rising edge of the DCSCLK pin. Data
are shifted in MSB first. The data are latched from the shift register into the DC data latch with a rising edge on
the XDCLAT pin.
Copyright © 2007, Texas Instruments Incorporated
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