TLC5941-Q1 Datasheet, PDF (19/27 Pages) Texas Instruments – 16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL

TLC5941-Q1
www.ti.com ........................................................................................................................................................................................... SLDS165 – DECEMBER 2008
STATUS INFORMATION OUTPUT
The TLC5941 does have a status information register, which can be accessed in grayscale mode (MODE =
GND). After the XLAT signal latches the data into the GS register, the input shift register data is replaced with
status information data (SID) of the device (see Figure 18). LOD, TEF, and dot-correction register data can be
read out at the SOUT pin. The status information data packet is 192 bits wide. Bits 0 – 15 contain the LOD status
of each channel. Bit 16 contains the TEF status. Bits 24 – 119 contain the data of the dot-correction register. The
remaining bits are reserved. The complete status information data packet is shown in Figure 19.
SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown in
Figure 20. The next SCLK pulse, which will be the clock for receiving the MSB of the next grayscale data,
transmits MSB-1 of SID. If output voltage is < 0.3 V (typical) when the output sink current turns on, LOD status
flag becomes active. The LOD status flag is an internal signal which pulls XERR pin down to low when the LOD
status flag becomes active. The delay time, tpd2 (1 µs maximum), is from the time of turning on the output sink
current to the time LOD status flag becomes valid. The timing for each channels LOD status to become valid is
shifted by the 30-ns (maximum), channel-to-channel turn-on time. After the first GSCLK goes high, OUT0 LOD
status is valid; tpd3 + tpd2 = 60 nS + 1 µs = 1.06 µs. OUT1 LOD status is valid; tpd3 + td + tpd2 = 60 ns + 30 ns
+ 1 µs = 1.09 µs. OUT2 LOD status is valid; tpd3 + 2*td + tpd2 = 1.12 µs, and so on. It takes 1.51µs maximum
(tpd3 + 15*td + tpd2) from the first GSCLK rising edge until all LOD become valid; tsuLOD must be > 1.51 µs
(see Figure 20) to ensure that all LOD data are valid.
MSB
0
15
16
23
24
LSB
119
120
191
LOD 15
LOD 0 TEF
X
X
DC 15.5
DC 0.0
X
X
LOD Data
TEF
DC Values
Figure 19. Status Information Data Packet Format
Reserved
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