TLC5941-Q1 Datasheet, PDF (16/27 Pages) Texas Instruments – 16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL

TLC5941-Q1
SLDS165 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
SETTING DOT CORRECTION
The TLC5941 has the capability to fine-adjust the output current of each channel (OUT0 to OUT15)
independently. This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs
connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit
word. The channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current I_max. The
TEST pin must be connected to VCC to ensure proper operation of the dot correction circuitry. Equation 8
determines the output current for each output n:
IOUTn + Imax
DCn
63
(8)
where:
I_max = the maximum programmable output current for each output.
DCn = the programmed dot correction value for output n (DCn = 0 to 63).
n = 0 to 15
Figure 15 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc. The DC
15.5 in Figure 15 stands for the 5^th-most significant bit for output 15.
MSB
0
5
6
DC 15.5
DC 15.0 DC 14.5
DC OUT15
DC OUT14 − DC OUT1
LSB
89
90
95
DC 1.0 DC 0.5
DC 0.0
DC OUT0
Figure 15. Dot Correction Data Packet Format
When MODE is set to VCC, the TLC5941 enters the dot correction data input mode. The length of input shift
register becomes 96bits. After all serial data are shifted in, the TLC5941 writes the data in the input shift register
to DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC register is a
level triggered latch of XLAT signal. Since XLAT is a level-triggered signal, SCLK and SIN must not be changed
while XLAT is high. After XLAT goes low, data in the DC register is latched and does not change. BLANK signal
does not need to be high to latch in new data. When XLAT goes high, the new dot-correction data immediately
becomes valid and changes the output currents if BLANK is low. XLAT has setup time (tsu1) and hold time (th1)
to SCLK as shown in Figure 12.
16
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