TLC5941-Q1 Datasheet, PDF (12/27 Pages) Texas Instruments – 16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL

TLC5941-Q1
SLDS165 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
PRINCIPLES OF OPERATION
SERIAL INTERFACE
The TLC5941 has a flexible serial interface, which can be connected to microcontrollers or digital signal
processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal
shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of XLAT
signal latches the serial data to the internal registers. The internal registers are level-triggered latches of XLAT
signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending on the
programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Although
new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscale
data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existing
grayscale data. Figure 12 shows the timing chart. More than two TLC5941s can be connected in series by
connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two
TLC5941s is shown in Figure 13. The SOUT pin can also be connected to the controller to receive status
information from TLC5941 as shown in Figure 22.
MODE
XLAT
DC Data Input Mode
th3
GS Data Input Mode
tsu3
twh2
SIN
DC
MSB
SCLK ¹
SOUT
BLANK
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
DC
LSB
th2
96
1st GS Data Input Cycle
GS1
MSB
tsu2
1
-
DC
-
-
MSB
tpd4
tpd1
GS1
LSB
tsu1
192
GS1
MSB
2nd GS Data Input Cycle
GS2
MSB
th1
twh0
193
1
GS2
LSB
192
twl0
SID1 SID1
MSB MSB-1
SID1 GS2
LSB MSB
GS3
MSB
tsu0
th0
193
1
tpd0
SID2 SID2
MSB MSB-1
twh3
1st GS Data Output Cycle
tsu5
1
tpd3
tpd3
th4
4096
Tgsclk
2nd GS Data Output Cycle
tsu4
twh1
1
twl1
tpd1 + td
td
tpd3 + td
touton
tpd1 + 15 x td
15 x td
tpd2
XERR
Figure 12. Serial Data Input Timing Chart
SIN(a )
SIN
SOUT
TLC5941 (a)
SIN
SOUT
TLC5941 (b)
SCLK, XLAT,
BLANK,
GSCLK,
MODE
Figure 13. Cascading Two TLC5941 Devices
SOUT(b )
12
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