PCI4410A Datasheet, PDF (189/198 Pages) Texas Instruments – PC CARD AND OHCI CONTROLLER

9.40 Isochronous Transmit Context Command Pointer Register
The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor
block that the PCI4410A device accesses when software enables an isochronous transmit context by setting bit 15
(run) in the isochronous transmit context control register (see Section 9.39) to 1. The n value in the following register
addresses indicates the context number (n = 0, 1, 2, 3, …, 7).
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Isochronous transmit context command pointer
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Isochronous transmit context command pointer
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Default:
Isochronous transmit context command pointer
Read-only
20Ch + (16 * n)
XXXX XXXh
9.41 Isochronous Receive Context Control Register
The isochronous receive context control set/clear register controls options, state, and status for the isochronous
receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).
See Table 9–31 for a complete description of the register contents.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Isochronous receive context control
Type
RSC RSC RSCU RSC R
R
R
R
R
R
R
R
R
R
R
R
Default X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Isochronous receive context control
Type
RSCU R
R RSU RU RU R
R RU RU RU RU RU RU RU RU
Default
0
0
0
X
0
0
0
0
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Default:
Isochronous receive context control
Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only
400h + (32 * n) set register
404h + (32 * n) clear register
X000 X0XXh
9–37