PCI4410A Datasheet, PDF (171/198 Pages) Texas Instruments – PC CARD AND OHCI CONTROLLER

9.22 Interrupt Mask Register
The interrupt mask set/clear register is used to enable the various PCI4410A interrupt sources. Reads from either
the set register or the clear register always return the contents of the interrupt mask register. In all cases except
masterIntEnable (bit 31), the enables for each interrupt event align with the event register bits detailed in Table 9–15.
See Table 9–16 for a description of the register contents.
Bit
31 30 29 28 27 26
25
24
23
22
21
20
19
18
17
16
Name
Interrupt mask
Type
RSC R R R R RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU R RSCU RSCU
Default 0
X0
0
0
X
X
X
X
X
X
X
X
0
X
X
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Interrupt mask
Type
R RRRR
R RSCU RSCU RU RU RSCU RSCU RSCU RSCU RSCU RSCU
Default 0
0000
0
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Default:
Interrupt mask
Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only
88h set register
8Ch clear register
XXXX 0XXXh
BIT
31
30–0
SIGNAL
masterIntEnable
Table 9–16. Interrupt Mask Register Description
TYPE
RSC
FUNCTION
If this bit is set to 1, external interrupts are generated in accordance with the interrupt mask register. If
this bit is cleared, no external interrupts are generated regardless of the interrupt mask register
settings.
See Table 9–15.
9–19