TMS320C6455_07 Datasheet, PDF (186/250 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6455
Fixed-Point Digital Signal Processor
SPRS276H – MAY 2005 – REVISED OCTOBER 2007
7.13.1 McBSP Device-Specific Information
The CLKS signal is shared by both McBSP0 and McBSP1 on this device. Also, the CLKGDV field of the
Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.
The McBSP Data Receive Register (DRR) and Data Transmit Register (DXR) can be accessed through
two separate busses: a configuration bus and a data bus. Both paths can be used by the CPU and the
EDMA. The data bus should be used to service the McBSP as this path provides better performance.
However, since the data path shares a bridge with the PCI and UTOPIA peripherals (see Figure 4-1), the
configuration path should be used in cases where these peripherals are being used to avoid any
performance degradation. Note that the PCI peripheral consists of an independent master and slave.
Performance degradation is only a concern when this peripheral is used to initiate transactions on the
external bus.
7.13.1.1 McBSP Peripheral Register Description(s)
HEX ADDRESS RANGE
028C 0000
3000 0000
028C 0004
3000 0010
028C 0008
028C 000C
028C 0010
028C 0014
028C 0018
028C 001C
028C 0020
028C 0024
028C 0028
028C 002C
028C 0030
028C 0034
028C 0038
028C 003C
028C 0040 - 028F FFFF
Table 7-57. McBSP 0 Registers
ACRONYM
DRR0
DRR0
DXR0
DXR0
SPCR0
RCR0
XCR0
SRGR0
MCR0
RCERE00
XCERE00
PCR0
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
-
REGISTER NAME
COMMENTS
McBSP0 Data Receive Register via Configuration Bus
The CPU and EDMA3
controller can only read
this register; they cannot
write to it.
McBSP0 Data Receive Register via EDMA3 Bus
McBSP0 Data Transmit Register via Configuration Bus
McBSP0 Data Transmit Register via EDMA Bus
McBSP0 Serial Port Control Register
McBSP0 Receive Control Register
McBSP0 Transmit Control Register
McBSP0 Sample Rate Generator register
McBSP0 Multichannel Control Register
McBSP0 Enhanced Receive Channel Enable
Register 0 Partition A/B
McBSP0 Enhanced Transmit Channel Enable
Register 0 Partition A/B
McBSP0 Pin Control Register
McBSP0 Enhanced Receive Channel Enable
Register 1 Partition C/D
McBSP0 Enhanced Transmit Channel Enable
Register 1 Partition C/D
McBSP0 Enhanced Receive Channel Enable
Register 2 Partition E/F
McBSP0 Enhanced Transmit Channel Enable
Register 2 Partition E/F
McBSP0 Enhanced Receive Channel Enable
Register 3 Partition G/H
McBSP0 Enhanced Transmit Channel Enable
Register 3 Partition G/H
Reserved
186 C64x+ Peripheral Information and Electrical Specifications
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