TMS320C6455_07 Datasheet, PDF (142/250 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6455
Fixed-Point Digital Signal Processor
SPRS276H – MAY 2005 – REVISED OCTOBER 2007
7.7.3.8 PLL Controller Clock Align Control Register
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-18 and described in
Table 7-26.
31
16
Reserved
R-0
15
Reserved
5
4
3
2
0
ALN5 ALN4
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
R-1 R-1
R-1
Figure 7-18. PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029A 0140]
Table 7-26. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit Field
31:5 Reserved
4:3 ALNn
2:0 Reserved
Value
0
0
1
0
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
SYSCLKn alignment. Do not change the default values of these fields.
Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set to 1,
SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set.
The SYSCLKn ratio is set to the ratio programmed in the RATIO bit in PLLDIVn.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
142 C64x+ Peripheral Information and Electrical Specifications
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