TLC59731 Datasheet, PDF (18/24 Pages) Texas Instruments – 3-Channel, 8-Bit, PWM LED Driver with Single-Wire Interface (EasySet)

TLC59731
SBVS222 – FEBRUARY 2013
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GS Data Latch (GSLAT) Sequence
A GS data latch (GSLAT) sequence must be input after the 32-bit data for all cascaded devices are written.
When SDI is held low for the data latch hold time (t_H1), the 32-bit shift register data in all devices are copied to
the GS data latch in each device. Furthermore, PWM control starts with the new GS data at the same time.
Figure 19 shows the GSLAT timing.
The first SDI rising edge of the last input data.
SDI
32-Bit Shift
Register
(Internal)
8 x t_CYCLE (min)
Shift register data are
written after GSLAT is input.
GSLAT Signal
(Internal)
GS Data in
24-Bit
Data Latch
(Internal)
OUTEN Signal
(Internal)
High = pulse signal output from SDO.
New GS Data
Low = pulse signal not output from SDO.
SDO
Figure 19. GS Data Latch Sequence (GSLAT)
18
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