BQ24040 Datasheet, PDF (18/31 Pages) Texas Instruments – 800mA Single-Input Single Cell Li-Ion Battery Charger With Auto Start

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SLUS941A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com
Power Good Indication (PG)
After application of a 5V source, the input voltage rises above the UVLO and sleep thresholds (V_IN>V_BAT+V_DT),
but is less than OVP (V_IN<V_OVP,), then the PG FET turns on and provides a low impedance path to ground. See
Figure 5, Figure 6, and Figure 18.
CHG Pin Indication
The charge pin has an internal open drain FET which is on (pulls down to V_SS) during the first charge only
(independent of TTDM) and is turned off once the battery reaches voltage regulation and the charge current
tapers to the termination threshold set by the PRE-TERM resistor.
The charge pin is high impedance in sleep mode and OVP (if PG is high impedance) and return to its previous
state once the condition is removed.
Cycling input power, pulling the TS pin low and releasing or entering pre-charge mode causes the CHG pin to go
reset (go low if power is good and a discharged battery is attached) and is considered the start of a first charge.
CHG and PG LED Pull-up Source
For host monitoring, a pull-up resistor is used between the "STATUS" pin and the V_CC of the host and for a visual
indication a resistor in series with an LED is connected between the "STATUS" pin and a power source. If the
CHG or PG source is capable of exceeding 7V, a 6.2V zener should be used to clamp the voltage. If the source
is the OUT pin, note that as the battery changes voltage, and the brightness of the LEDs vary.
Charging State
1st Charge
Refresh Charge
OVP
SLEEP
TEMP FAULT
CHG FET/LED
ON
OFF
ON for 1st Charge
V_IN Power Good State
UVLO
PG FET/LED
SLEEP Mode
OFF
OVP Mode
Normal Input (V_OUT + V_DT < V_IN <
V_OUP)
ON
PG is independent of chip disable
Auto Start-up (bq24041)
The auto start-up feature is an OR gate with two inputs; an internal power good signal (logic 1 when V_IN>V_BAT +
V_IN-DT) and an external input from ASI pin (internal 100k pull-down). The ASO pin outputs a signal that can be
used as a system boot signal. The OR gate is powered by the OUT pin and the OUT pin must be powered by an
external source (battery or P/S) or via the IN pin for the ASO pin to deliver a logic High. The ASI and/or the
internal power good signal have to be logic high for the ASO to be logic high. The ASI/ASO, OUT and PG signals
are used in production testing to test the system without a battery.
IN-DPM (V_IN-DPM or IN-DPM)
The IN-DPM feature is used to detect an input source voltage that is folding back (voltage dropping), reaching its
current limit due to excessive load. When the input voltage drops to the V_IN-DPM threshold the internal pass FET
starts to reduce the current until there is no further drop in voltage at the input. This would prevent a source with
voltage less than V_IN-DPM to power the out pin. This works well with current limited adaptors and USB ports as
long as the nominal voltage is above 4.3V and 4.4V respectively. This is an added safety feature that helps
protect the source from excessive loads.
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