ADS62P15 Datasheet, PDF (18/57 Pages) Texas Instruments – Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

ADS62P15
SLAS572 – OCTOBER 2007
www.ti.com
Table 4.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
12
0
0
<LVDS TERMINATION> Internal termination programmability
D5–D3
000
001
010
011
100
101
110
111
D2–D0
000
001
010
011
100
101
110
111
<LVDS DATA TERM> Internal termination control for data outputs
No internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
<LVDS CLK TERM> Internal termination control for clock output
No internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
A7–A0
(hex)
13
D4
0
1
Table 5.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
<OFFSET FREEZE>
0
0
0
0
<OFFSET FREEZE> Offset correction becomes inactive and the last estimated offset value is used to cancel the offset
Offset correction active
Offset correction inactive
18
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