ADS62P15 Datasheet, PDF (17/57 Pages) Texas Instruments – Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

ADS62P15
www.ti.com
DESCRIPTION OF SERIAL REGISTERS
Table 1.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
00
0
0
0
0
0
0
D1
<RST>
1
Software reset applied – resets all internal registers and self-clears to 0.
SLAS572 – OCTOBER 2007
D1
D0
<RST>
Software Reset
0
Table 2.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
10
<CLKOUT STRENGTH>
0
0
0
0
0
0
D7–D6
01
00
11
10
<CLKOUT STRENGTH> Output clock buffer drive strength control
WEAKER than default drive
DEFAULT drive strength
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
A7–A0
(hex)
11
D1–D0
01
00
11
10
D3–D2
00
01
10
11
D5–D4
00
01
10
11
Table 3.
D7
D6
D5
D4
D3
D2
0
0
<CURRENT DOUBLE>
LVDS buffer current double
LVDS CURRENT> LVDS
buffer current
programmability
<DATAOUT STRENGTH> Output data buffer drive strength control
WEAKER than default drive
DEFAULT drive strength
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
<LVDS CURRENT> LVDS Current programmability
3.5 mA
2.5 mA
4.5 mA
1.75 mA
CURRENT DOUBLE> LVDS Current double control
default current, set by <LVDS CURR>
LVDS clock buffer current is doubled, 2x <LVDS CURR>
LVDS data and clock buffers current are doubled, 2x <LVDS CURR>
unused
D1
D0
DATAOUT STRENGTH>
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS62P15
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