OMAP3525-HIREL Datasheet, PDF (173/239 Pages) Texas Instruments – OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

www.ti.com
OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
SPRS599 – JUNE 2009
6.5.2 Display Subsystem (DSS)
The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or
internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller, a remote
frame buffer module (RFBI), and a TV-out module. It can be used in two configurations:
• LCD display in:
– Bypass mode (RFBI module bypassed)
– RFBI mode (through RFBI module)
• TV display (not discussed in this document because of its analog IO signals)
The two displays can be active at the same time.
NOTE
For more information, see Display Subsystem / Display Subsystem Functional Description
section of the OMAP35x Technical Reference Manual (TRM) [literature number
SPRUF98.
6.5.2.1 LCD Display in Bypass Mode
Two types of LCD panel are supported:
• Thin film transistor (TFT) or active matrix technology
• Supertwisted nematic (STN) or passive matrix technology
Both configurations are discussed in the following paragraphs.
6.5.2.1.1 LCD Display in TFT Mode
6.5.2.1.1.1 LCD Display in TFT Mode – HDTV Application
Table 6-44 assumes testing over the recommended operating conditions (see Figure 6-32).
Table 6-44. LCD Display Switching Characteristics in TFT Mode – HDTV Application^(3)(4)(5)
NO.
PARAMETER
OPP3
OPP2
UNIT
MIN
MAX
MIN
MAX
DL0 t_{d(PCLKA-HSYNCT)} Delay time, dss_pclk active edge to dss_hsync –4.2
4.2
–4.7
4.7
ns
transition
DL1 t_{d(PCLKA-VSYNCT)} Delay time, dss_pclk active edge to dss_vsync –4.2
4.2
–4.7
4.7
ns
transition
DL2 t_{d(PCLKA-ACBIASA)} Delay time, dss_pclk active edge to
dss_acbias active level
–4.2
4.2
–4.7
4.7
ns
DL3 t_{d(PCLKA-DATAV)} Delay time, dss_pclk active edge to dss_data
–4.2
4.2
–4.7
4.7
ns
bus valid
DL4
DL5
t_c(PCLK)
t_w(PCLK)
Cycle time⁽²⁾, dss_pclk
Pulse duration, dss_pclk low or high
13.468
15.152
ns
0.45*P⁽¹⁾ 0.55*P⁽¹⁾ 0.45*P⁽¹⁾ 0.55*P⁽¹⁾
ns
(1) P = dss_pclk period.
(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the
DISPC_DIVISOR register.
(3) The capacitive load is equivalent to 25 pF at 1.15 V and 30 pF at 1.0 V.
(4) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98.
(5) See DM Operating Condition Addendum for OPP voltages.
Submit Documentation Feedback
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 173